Semiconductor memory device and method for arranging memory...

Details Semiconductor memory device and method for arranging memory... Semiconductor memory device and method for arranging memory...

2005-02-22

2005-02-22

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Fet configuration adapted for use as static memory cell

Reexamination Certificate

active

06858949

ABSTRACT:
A memory cell array of a semiconductor memory device includes a first sub array configured by a plurality of first cell units, a second sub array configured by a plurality of second cell units, and a non-memory cell region used for a backgate and arranged between the two sub arrays. Memory cells located on each side of the non-memory cell region are oriented in the same direction. Pairs of bit lines have substantially the same number of bit line contacts.

REFERENCES:
patent: 6373107 (2002-04-01), Nikaido
patent: 08-274271 (1996-10-01), None

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