Semiconductor memory device and memory system

Details Semiconductor memory device and memory system Semiconductor memory device and memory system

1998-08-31

1999-10-19

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

36523003, 365229, 36518905, 365222, H01L 2710

Patent

active

059699965

ABSTRACT:
Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.

REFERENCES:
patent: 5426603 (1995-06-01), Nakamara et al.
patent: 5508960 (1996-04-01), Pinkham
patent: 5511031 (1996-04-01), Grover et al.
patent: 5701269 (1997-12-01), Fujii
patent: 5796671 (1998-08-01), Wahlstrom
patent: 5818784 (1998-10-01), Muranaka et al.

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