Semiconductor memory device and memory access system using a fou

Details Semiconductor memory device and memory access system using a fou Semiconductor memory device and memory access system using a fou

1994-04-13

1996-07-16

Nelms, David C.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518901, 36523008, 36523003, 365227, G11C 800

Patent

active

055373615

ABSTRACT:
The disclosed is an DRAM which is accessible in response to four-state address signal. A two-state address signal generator receives the four-state address signal respectively defined by four voltage levels and converts it to a row address signal and a column address signal which are two-state address signals. Converted address signals are supplied to a row decoder and a column decoder, respectively. Address signals for access are supplied without adopting an address multiplexing system, so that it is possible to perform accurate addressing under the requirement of high speed operation. In addition, the number of sense amplifiers to be activated in one read operation can be reduced, and therefore power consumption can be also reduced.

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"Method for Addressing a Two-Dimensional Memory with Address Incrementing Random-Access Memories", IBM Technical Disclosure Bulletin, vol. 29, No. 9, Feb. 1987, pp. 4212-4215.

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