Semiconductor memory device and manufacturing method thereof

Details Semiconductor memory device and manufacturing method thereof Semiconductor memory device and manufacturing method thereof

2002-07-26

2004-09-14

Blum, David S. (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S304000, C257S311000

Reexamination Certificate

active

06791134

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a semiconductor memory device and a manufacturing method thereof, in detail relates to a semiconductor memory device which can be miniaturized and its manufacturing method in which such a semiconductor memory device can be manufactured readily and precisely.
BACKGROUND ART
A semiconductor memory device used in great volume for a personal computer, a workstation, a main frame computer and others is a dynamic random access memory (hereinafter called DRAM) consisting of one transistor which functions as a switch and one capacitor as the smallest unit. This DRAM has been heretofore enhanced in the ratio of four times in three years in the degree of integration and at present, the mass production of a 64-megabit DRAM which is to be manufactured using micro-fabrication technology in the next generation and the minimum feature size of which is 0.35 &mgr;m is being developed.
Heretofore, the high integration of a semiconductor memory device has been achieved by reducing the device size, however, the amount of charge which can be stored in a capacitor as information is reduced because the area of the capacitor is reduced for miniaturization. As a result, as signal to noise ratio is deteriorated and reliability is deteriorated because a problem such as the signal reversal caused by the incidence of alpha rays occurs, it is indispensable and the greatest task of a semiconductor memory device to secure the sufficient stored charge so as to keep reliability.
The amount of charge stored in a capacitor is determined by the product of the capacity of the capacitor and applied voltage, the capacity of the capacitor is proportional to the area of the capacitor and the dielectric constant of the dielectric film of the capacitor and is inversely proportional to the thickness of the capacitor dielectric film. Therefore, a stacked-type capacitor wherein a part of a capacitor is formed on the switching transistor and an oxide film for device isolation and a trench-type capacitor wherein a deep trench is formed on a semiconductor substrate and the side wall of the trench is utilized as a capacitor are used in a memory device (hereinafter called a memory cell) of a 4- or more-megabit DRAM so as to prevent storage capacity from being reduced by the reduction of the area of a capacitor caused by microminiaturization. A 64-megabit DRAM can be realized by using a capacitor with such structure.
However, when the area of a memory cell is reduced in the ratio of ⅓of the previous generation according to a trend, even a memory cell using a stereoscopic capacitor such as the stacked-type capacitor and trench-type capacitor cannot compensate the reduction of the area of the capacitor completely and it is difficult to secure required capacity.
To solve such a problem, a charge storage capacitor called a crown type is proposed. This crown-type capacitor is a stereoscopic one utilizing the inner and outer walls of a concave (crown-type) electrode
19
shown in
FIG. 2
as the electrode of the capacitor. Referring to
FIG. 2
, a reference number
1
denotes a semiconductor substrate,
2
denotes an oxide film for device isolation,
3
denotes the gate oxide film of a transistor,
4
denotes the gate electrode of the switching transistor,
5
and
5
′ denote a diffused region different from the substrate in a conductivity type,
6
denotes an interlayer dielectric film,
7
denotes a bit line connected to the diffused region
5
′,
8
denotes an interlayer dielectric film,
13
denotes metal for connecting the diffused region
5
and the lower electrode of a capacitor,
19
denotes the lower electrode of the capacitor,
20
denotes a capacitor dielectric film,
21
denotes a plate electrode of the capacitor,
22
denotes an interlayer dielectric film,
23
denotes wiring connected to the diffused region of the substrate,
24
denotes an interlayer dielectric film and
25
denotes the uppermost wiring.
Storage capacity can be increased by adopting structure using such a crown-type capacitor electrode
19
for the capacitor of a DRAM, however, not only an extremely complicated process is required to realize such structure, but there exists a problem that there is great step height.
That is, as shown in
FIG. 2
, great step height is caused by the crown-type electrode
19
between a memory cell (a left section in
FIG. 2
) and a transistor (a right section in
FIG. 2
) in the vicinity and as a result, it is difficult to form wiring
23
on this step height. As the depth of the focus of a used reduction projection aligner is shallow and the tolerance of the focus (depth of focus) is small in optical lithography used for forming wiring
23
with a predetermined pattern, this is because it is difficult to focus on both the upper and lower portions of the step height suitably. In addition, this is because the smaller the dimension of a pattern is, the smaller depth of focus is and a range in which a focus is suitably adjusted is further smaller.
To solve such a problem in forming a wiring pattern caused by step height, a method of planarizing the surface of a substrate by a chemical mechanical polishing (CMP) method is proposed and is already applied to planarizing the interlayer dielectric film of the multilayer interconnection of a logic large scale integrated circuit (LSI).
However, it is difficult to apply this CMP method to a substrate wherein the crown-type electrode
19
approximately 1 &mgr;m in height is already formed for a variety of reasons. First of all, when mechanical polishing by applying mechanical force is applied to a capacitor wherein a very thin capacitor dielectric film is formed, possibility that a pinhole or a crack is made on the capacitor dielectric film and as a result, failure of electric isolation occurrence is high. Secondly, the internal stress of a thick oxide film is caused because an oxide film with at least a double thickness of step height is required so as to bury a capacitor with large step height in the oxide film and thus failure of electric insulation of the capacitor dielectric film is caused by this large internal stress as described.
A method of lowering the surface of a silicon substrate in a memory cell array in an initial process is proposed in Japanese published unexamined patent application No. Sho 63-266866. However, if step height is large, the method is difficult to apply.
A memory cell provided with the crown-type capacitor is described in Japanese published unexamined patent applications No. Sho62-48062 and No. Sho62-1281268.
FIG. 73
shows the plane arrangement of this memory cell and
FIG. 74
shows the section viewed along a line X-X′ in FIG.
73
and the section of the main part of peripheral circuits. The structure of the section shown in
FIG. 75
is a prior embodiment utilizing the internal face of a storage electrode in a trench as a capacitor. This structure has an advantage that it is easier in manufacturing than a crown-type capacitor.
Referring to
FIGS. 73
,
74
and
75
, a reference number
101
denotes a silicon substrate,
102
denotes a field oxide film,
103
,
104
and
105
denote highly concentrated impurity regions which are a source or a drain,
106
and
107
denote gate electrodes,
111
denotes a storage electrode,
112
denotes the dielectric film of a capacitor,
113
denotes a plate electrode,
114
denotes a silicon oxide film,
127
denotes an active area,
128
denotes a word line,
130
denotes a data line,
129
denotes a contact hole and
131
denotes a connecting hole. As shown in
FIGS. 74 and 75
, these conventional semiconductor memories wherein a capacitor is formed on a silicon substrate have large step height between a memory cell and its peripheral circuits.
In a trench capacitor cell wherein a capacitor is formed inside a substrate, large step height is not formed on the substrate. Since the storage capacity can be increased by deepening a trench formed on a substrate, the capacity of the storage capacitor can be prevented from being reduced by reducin

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