Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-04-19
2003-07-22
Eckert, George (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S309000
Reexamination Certificate
active
06597033
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a manufacturing method thereof, and more particularly, relates to a semiconductor memory device having a capacitor in which lamination is performed like a cylinder over a semiconductor substrate, a so-called cylindrical stack-type capacitor, and a manufacturing method thereof.
2. Description of the Prior Art
Recently, in case of a semiconductor device such as a DRAM (Dynamic Random Access Memory) or the like, in order to realize a high integration, it is required to increase an electrostatic capacity per occupied area of a capacitor configuring each memory cell. Therefore, complying with this request, a capacitor having a stereo-structure such as a stack-type capacitor formed by performing lamination over a substrate or a trench-type capacitor formed by digging a substrate deeply is often used. At this moment, means for increasing the electrostatic capacity by shaping a storage electrode (lower electrode) configuring each capacitor like a cylinder is employed.
Furthermore, for an electrode material of a capacitor, polysilicon is often used, and an attempt is also made, in which a lot of hemi-spherical grained silicon (hereafter, referred to as HSG) is formed on the surface of this polysilicon electrode and the surface area of the electrode is increased by making the surface uneven so that the electrostatic capacity may be increased.
As one example of this type of capacitor structure, a structure in which a capacitor is made in a recess provided in an insulator film over the substrate is disclosed in Japanese Patent Laid-Open No. 10-79478 or the like. This type of conventional DRAM memory cell is shown in
FIG. 8A
to FIG.
8
C.
FIG. 8A
to
FIG. 8C
especially shows the processes of forming a storage electrode which is one electrode of a capacitor in order. As shown in
FIG. 8A
, a transistor
104
having a gate electrode
101
and n-type impurity diffusion layers
102
,
103
of the source and drain areas is formed on a silicon substrate
100
, and after that, a first interlayer insulator film
105
is formed on the entire surface. Next, a bit contact hole
106
which penetrates the first interlayer insulator film
105
to reach the n-type impurity diffusion layer
102
is formed, and a bit line
107
electrically connected to the n-type impurity diffusion layer
102
through the bit contact hole
106
is formed.
Next, a second interlayer insulator film
108
is formed on the entire surface, and a capacity contact hole
109
which penetrates the second interlayer insulator film
108
and the first interlayer insulator film
105
to reach the n-type impurity diffusion layer
103
is formed, and after that, the capacity contact hole
109
is filled up with polysilicon. Next, a third interlayer insulator film
110
is formed on the entire surface, and after that, this is patterned to form a recess
110
a at a capacitor forming place. Then, a polysilicon film is formed on the entire surface, and after that, the polysilicon film on the upper surface of the third insulator film
110
is removed by chemical mechanical polishing (hereafter referred to as CMP), and in the meantime, the polysilicon film is left being shaped like a cylinder only on the side and the bottom surface of the recess
110
a
, and this is made to be a storage electrode
111
. By the way, it is usual to use a material of the silicon oxide film family such as SiO
2
or BPSG for an interlayer insulator film such as the first interlayer insulator film
105
, the second interlayer insulator film
108
, or the third interlayer insulator film
110
.
An original form of a storage electrode is completed up to the process shown in the above described
FIG. 8A
, and here, in order to enlarge the surface area of the storage electrode so that the capacity of a capacitor may be increased, HSG is formed on the surface of a polysilicon film of the storage electrode. At the time of reaction of the HSG formation, a movement of silicon atoms in the polysilicon film is accompanied, and here, if an oxide film is formed on the surface of the polysilicon film, the movement of the silicon atoms is prevented by the existence of the oxide film, and there are some cases where HSG with a sufficient grain diameter does not grow.
By the way, in the manufacturing process, when a time of a certain extent elapses in the state where the polysilicon film is exposed, a natural oxide film of some nm or less is formed on the surface of the polysilicon film. However, as mentioned above, this natural oxide film becomes a factor to prevent the growth of HSG, and therefore, usually, as a pretreatment of the HSG formation process, removing of the natural oxide film on the surface of the polysilicon film is performed. In this pretreatment process, it is usual to perform removing of the natural oxide film by soaking a wafer in the etchant including hydrofluoric acid often used for removing a silicon oxide film in the semiconductor manufacturing process.
However, in the wafer which has passed through this HSG pretreatment process, not only the natural oxide film on the surface of the polysilicon film is removed, but also as shown in
FIG. 8B
, the third interlayer insulator film
110
exposed to the uppermost surface is also a little etched, and the state becomes a state where the upper end of the cylindrical storage electrode
111
is a little projecting from the upper surface of the third interlayer insulator film
110
. In this state, when the heat treatment of the wafer is performed in a gaseous atmosphere containing silicon, as shown in
FIG. 8C
, HSG
112
is formed on the entire exposed surface of the polysilicon film of the storage electrode
111
.
In the case where two capacitors close to each other exist in a memory cell array, before the HSG pretreatment, as shown in
FIG. 8A
, both storage electrodes
111
are completely separated by the third interlayer insulator film
110
, but after the HSG pretreatment, as shown in
FIG. 8B
, the upper surface of the third interlayer insulator film
111
retreats, and therefore, the outer surface sides of the fellow upper ends of both storage electrodes
111
face to each other (place indicated by the mark C). Here, when the HSG treatment is performed, as shown in
FIG. 8C
, the HSG
112
is also formed on this outer surface side, and therefore, the state becomes a state where the fellow HSG's
112
of the upper end outer surfaces of these two adjacent storage electrodes
111
are close to each other. In some cases, there has been a probability that these HSGIs, that is, the storage electrodes cause a failure of a short circuit and that the yield is lowered.
In future, as the fining of a DRAM is improved, when the space between the adjacent memory cells is narrowed, the space between the capacitors requiring a large occupied area in the memory cell naturally cannot also help being narrowed, and in the design, the case where two storage electrodes are arranged extremely close to each other is increased. Usually, the grain diameter of HSG is about 0.05 to 0.1 &mgr;m, and therefore, in order to that the fellow HSG's of the adjacent storage electrodes may not cause a short circuit, the space between the adjacent storage electrodes must be designed to have a wide length, for example, 0.3 &mgr;m with a margin of some extent, and it results in giving a limit to the fining of a memory cell. That is, a conflicting situation has been made, in which at the time of performing the fining of a memory cell, in order to ensure a specific capacity in the limited occupied area, a method of forming HSG in the storage electrode is employed but on the other hand, the formation of HSG gives a limitation to the fining of a memory cell in reverse, in the adjacent storage electrodes.
BRIEF SUMMARY OF THE INVENTION
OBJECT OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory device with a structure by which in a capacitor with a cylindrical lower electrode having H
Eckert George
McGinn & Gibb PLLC
NEC Corporation
LandOfFree
Semiconductor memory device and manufacturing method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device and manufacturing method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device and manufacturing method thereof will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3103308