Semiconductor memory device and manufacturing method thereof

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257319, 257321, 257368, 257403, 257404, H01L 2968, H01L 2978, H01L 2986

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active

052432106

ABSTRACT:
A semiconductor memory device having a non-volatile memory transistor and a selection transistor formed near the non-volatile memory transistor. The channel region surface of the memory transistor is formed to have the same conductivity type with a lower density than the channel region surface of the selection transistor or opposite conductivity type so that the characteristic of the memory transistor shifts to the negative side resulting in a sufficient read margin for an erased cell even at a control voltage of 0.

REFERENCES:
patent: 3952325 (1976-04-01), Beale et al.
patent: 4398338 (1983-08-01), Tickle et al.
patent: 4402064 (1983-08-01), Arakawa
patent: 4462090 (1984-07-01), Iiznka
patent: 4752912 (1988-06-01), Guterman
"High-Voltage Regulation and Process Considerations for High-Density 5 V-Only E.sup.2 PROM's", Duane H. Oto et al., IEEE Journal of Solid State Circ., vol. SC-18 Oct. 1983.
"Analysis and Modeling of Floating-Gate EEPROM Cells", Avinoam Kolodny et al, IEEE Transaction on Electron Devices, vol. ED-33, No. 6, Jun. 1966.

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