Semiconductor memory device and manufacturing method therefor

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S202000, C257S298000, C257S314000, C257S324000, C257S326000, C257S900000, C257S909000

Reexamination Certificate

active

06936891

ABSTRACT:
A semiconductor memory device, adapted for storing plural bits per cell to be able to accomplish high storage density by a simplified structure, includes a plurality of first gate electrodes extending parallel to one another along one direction and a plurality of second gate electrodes extending in a direction of intersecting the first gate electrodes, in which a diffusion region is provided on each of a plurality of divisions demarcated in a matrix-like pattern by first and second electrodes on a substrate surface. One of the divisions, the four sides of which are defined by two neighboring first gate electrodes and two neighboring second gate electrodes, has four independently accessible bits, and is connected by a contact (CT) with a diffusion region in the division. There are provided a plurality of interconnections connected via contacts to the diffusion regions of other divisions in the plural matrix-like divisions lying on the line of extension of the aforementioned diagonal line. A plurality of the aforementioned interconnections are arranged for extending parallel to one another in the memory cell array in an oblique direction relative to the lattice of the first and second electrodes.

REFERENCES:
patent: 5745007 (1998-04-01), Redman-White
patent: 5768192 (1998-06-01), Eitan
patent: 5985718 (1999-11-01), Dalla Libera et al.
patent: 6181597 (2001-01-01), Nachumovsky
patent: 6269023 (2001-07-01), Derhacobian et al.
patent: 6346442 (2002-02-01), Aloni et al.
patent: 2003/0082871 (2003-05-01), Harari et al.
patent: 64-073761 (1989-03-01), None
patent: 2001-512290 (2001-08-01), None
patent: WO 99/07000 (1999-02-01), None

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