Semiconductor memory device and manufacturing method of the...

Details Semiconductor memory device and manufacturing method of the... Semiconductor memory device and manufacturing method of the...

2007-11-06

2007-11-06

Fahmy, Wael (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Total dielectric isolation

C438S459000, C257SE21567

Reexamination Certificate

active

11236668

ABSTRACT:
In this semiconductor memory device, a potential clamping region having no insulation layer formed therein is provided in an insulation layer. More specifically, the potential clamping region is formed under a body portion at a position near a first impurity region, and extends to a first semiconductor layer. A body fixing portion is formed in a boundary region between the body portion and the potential clamping region. This structure enables improvement in operation performance without increasing the layout area in the case where a DRAM cell is formed in a SOI (Silicon On Insulator) structure.

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