Semiconductor memory device and manufacturing method for the...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257SE29309

Reexamination Certificate

active

07315059

ABSTRACT:
The present invention provides a semiconductor memory device having one or more protruding semiconductor layers formed on a semiconductor substrate of a first conductivity type and a plurality of memory cells on surfaces of the protruding semiconductor layers, wherein each of the memory cells is formed of a charge storage layer, a control gate and an impurity diffusion layer of a second conductivity type which is formed in a portion of the protruding semiconductor layer and the plurality of memory cells is aligned to at least a predetermined direction, and the control gates of the plurality of memory cells is aligned to the predetermined direction are placed so as to be separated from each other.

REFERENCES:
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patent: 2002/0096703 (2002-07-01), Vora
patent: 2003/0075756 (2003-04-01), Suzuki
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patent: 2001-077220 (2001-03-01), None
Chen, J. T-Y. et al. (2000). “A New Dual Floating Gate Flash Cell for Multilevel Opertion,”Extended Abstracts of the 2000 International Conference on Solid State Devices and Materials, Abstract C-5-4, pp. 282-283.
Endoh et al. (2003) “Novel Ultrahigh-Density Flash Memory With a Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”IEEE Transactions On Electron Devices50 (4): 945-951.
Endoh et al. (2001) “Novel Ultra High Density Flash Memory With a Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”IEEE: 33-36.
European Search Report dated May 25, 2007, directed to counterpart EP application 04253144.2 (4 pages).

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