Semiconductor memory device and layout structure of sub-word...

Details Semiconductor memory device and layout structure of sub-word... Semiconductor memory device and layout structure of sub-word...

2008-07-22

2010-12-14

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230080, C365S230030

Reexamination Certificate

active

07852703

ABSTRACT:
A semiconductor memory device and a layout structure of sub-word line control signal generators. The sub-word line control signal generators are configured to supply a sub-word line control signal of a predefined voltage level to a sub-word line driver to enable a sub-word line of a memory cell array. At least two sub-word line control signal generators are disposed, respectively, at edge areas of the memory cell array, to directly supply the sub-word line control signal to one selected sub-word line driver, thereby reducing the power consumption, including for example, VPP voltage. Embodiments of the present invention also reduce the number of VPP power lines, thereby lessening a noise disturbance.

REFERENCES:
patent: 6747908 (2004-06-01), Lee et al.
patent: 2006/0171242 (2006-08-01), Yoon et al.
patent: 11-354744 (1999-12-01), None
patent: 2006-0082499 (2006-07-01), None
English language abstract of Japanese Publication No. 11-354744.
English language abstract of Korean Publication No. 2006-0082499.

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