Semiconductor memory device and layout method thereof

Details Semiconductor memory device and layout method thereof Semiconductor memory device and layout method thereof

2001-08-27

2002-07-30

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230010, C365S230060, C365S230080

Reexamination Certificate

active

06426913

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a layout method for a semiconductor memory device. More specifically, the present invention provides a semiconductor memory device and a layout method for arranging a semiconductor memory device without increasing chip size while increasing memory capacity.
2. Description of the Related Art
In a conventional layout method for arranging signal lines of memory cell arrays in a semiconductor memory device, word lines and I/O lines are disposed in the same direction with each other. Column select signal lines and bit lines are disposed in a row direction as intersecting the word lines. This general signal line layout method can integrate many memory cells.
However, in recent years, it has become necessary for a semiconductor memory device to include a number of data I/O lines that is more than the number of column select signal lines, in order to increase the number of bits transferred per second, in accordance with the development of graphic fields. Accordingly, a layout method for arranging signal lines different from the conventional layout method is used in the graphic fields. That is, in the layout method of the graphic fields, word lines and column select signal lines are disposed in the same direction with each other, and bit lines and I/O lines are disposed as intersecting the word lines.
FIG. 1
is a block diagram illustrating one type of a conventional semiconductor memory device. The device includes memory cell array blocks
10
-
1
,
10
-
2
, . . . , and
10
-
8
, row decoders
12
-
1
,
12
-
2
, . . . , and
12
-
8
, column decoders
14
-
1
,
14
-
2
, . . . , and
14
-
9
, and column predecoder
16
. Column select signal lines CSL
0
, CSL
1
, CSL
2
and CSL
3
are disposed in a row direction. I/O line pairs(IO
1
, IO
1
B), (IO
2
,IO
2
B), . . . , and (IOm, IOmB) are disposed in a column direction as intersecting the column select signal lines CSL
0
, CSL
1
, CSL
2
and CSL
3
. The column select signal lines are commonly connected to two adjacent memory cell array blocks. For example, the column select signal lines CSL
2
and CSL
3
between the memory cell array blocks
10
-
1
and
10
-
2
select the memory cell array block
10
-
1
when the memory cell array block
10
-
1
is activated, or select the memory cell array block
10
-
2
when the memory cell array block
10
-
2
is activated.
Eight row decoders
12
-
1
,
12
-
2
, . . . , and
12
-
8
input and decode row address RA
0
-k of k bits, the row decoders
12
becoming active in response to block select signals BLS
0
, BLS
1
, . . . , and BLS
7
.
The column predecoder
16
generates decoding output signals CA
0
B
1
B, CA
01
B, CA
0
B
1
, and CA
01
by decoding column address CA
0
and CA
1
. Responding to the block select signal BLS
0
at a high level, the column decoder
14
-
1
activates the column select signal line CSL
0
when the decoding output signal CA
0
B
1
B is at a high level and activates the column select signal line CSL
1
when the decoding output signal CA
01
B is at a high level. Responding to the block select signal BLS
7
at a high level, the column decoder
14
-
9
activates the column select signal line CSL
0
when the decoding output signal CA
0
B
1
B is at a high level or activates the column select signal line CSL
1
when the decoding output signal CA
01
B is at a high level. Responding to the block select signal BLS
0
or BLS
1
at a high level, the column decoder
14
-
2
activates the column select signal line CSL
2
when the decoding output signal CA
0
B
1
is at a high level or activates the column select signal line CSL
3
when the decoding output signal CA
01
is at a high level. The column decoders
14
-
3
, . . . , and
14
-
8
activate the column select signal lines CSL
0
, CSL
1
, CSL
2
and CSL
3
with the same method as the column decoder
14
-
1
or
14
-
2
.
FIG. 2
is a circuit diagram illustrating one configuration of the column predecoder
16
of FIG.
1
. The column predecoder
16
includes inverters I
1
, I
2
, I
3
, I
4
, I
5
and I
6
, and NAND gates NA
1
, NA
2
, NA
3
and NA
4
. The inverters I
1
and I
2
invert the column address CA
0
and CA
1
, respectively. The circuit including NAND gate NA
1
and inverter I
3
generates the decoding output signal CA
0
B
1
B at a high level when inputting output signals of the inverters I
1
and I
2
at a high level. The circuit including NAND gate NA
2
and inverter I
4
generates the decoding output signal CA
01
B at a high level when inputting output signals of the column address CA
0
and inverter I
2
at a high level. The circuit including NAND gate NA
3
and inverter I
5
generates the decoding output signal CA
0
B
1
at a high level when inputting an output signal of the inverter I
1
and the column address CA
1
at a high level. The circuit including NAND gate NA
4
and inverter I
6
generate the decoding output signal CA
01
by inputting the column addresses CA
0
and CA
1
at a high level.
FIG. 3
is a circuit diagram illustrating one configuration of one of the column decoders
14
of FIG.
1
. The column decoders
14
each include a NOR gate NOR
1
, inverters I
7
, I
8
and I
9
, and NAND gates NA
5
and NA
6
. In
FIG. 3
, signals C
1
and C
2
denote two block control signals applied to each of the column decoders
14
-
1
,
14
-
2
, . . . , and
14
-
9
of FIG.
1
. Signals I
1
and I
2
denote two decoding output signals (CA
0
B
1
B, CA
01
B) and (CAOB
1
, CA
01
), respectively, applied to each of the column decoders
14
-
1
,
14
-
2
, , and
14
-
9
of FIG.
1
. Signals O
1
and O
2
denote two column select signals output from each of the column decoders
14
-
1
,
14
-
2
, . . . , and
14
-
9
of FIG.
1
.
Operation of the circuit illustrated in
FIG. 3
will now be described. The circuit including NOR gate NOR
1
and inverter I
7
generates an output signal at a high level in the case in which at least one signal of signals C
1
and C
2
is at a high level. The circuit including NAND gate NA
5
and inverter I
8
outputs the input signal I
1
as the output signal O
1
by responding to an output signal of the inverter I
7
at a high level. The circuit including NAND gate NA
6
and inverter I
9
outputs the input signal I
2
as the output signal O
2
by responding to an output signal of the inverter I
7
at a high level.
FIG. 4
is a detailed block diagram illustrating one configuration of the memory cell array block
10
-
2
of FIG.
1
. The memory cell array block includes memory cells
20
-
11
,
20
-
12
, . . . ,
20
-
1
(
4
m
),
20
-
21
,
20
-
22
, ,
20
-
2
(
4
m
), . . . ,
20
-
n
1
,
20
-
n
2
, . . . , and
20
-
n
(
4
m
), precharge circuits
22
-
1
,
22
-
2
, . . . , and
22
-(
4
m
), sense amplifiers
24
-
1
,
24
-
2
, . . . , and
24
-(
4
m
), and I/O gates IOG
1
, IOG
2
, , and IOG(
4
m
).
Word lines WL
1
, WL
2
, . . . , and WLn of the memory cell array block
10
-
2
are disposed in the same direction as the column select signal lines CSL
0
, CSL
1
, CSL
2
and CSL
3
. Bit line pairs (BL
1
, BL
1
B), (BL
2
, BL
2
B), . . . , and (BL(
4
m
), BL(
4
m
)B) are disposed in the same direction as I/O line pairs (IO
1
, IO
1
B), . . . , and (IOm, IomB).
Also, the memory cells
20
-
11
,
20
-
12
, . . . ,
20
-
1
(
4
m
),
20
-
21
,
20
-
22
, . . . ,
20
-
2
(
4
m
), . . . ,
20
-
n
1
,
20
-
n
2
, . . . , and
20
-
n
(
4
m
) are connected between the word lines WL
1
, WL
2
, . . . , and WLn and bit line pairs (BL
1
, BL
1
B), (BL
2
, BL
2
B), . . . , and (BL(
4
m
), BL(
4
m
)B), respectively. The I/O gate IOG
1
, I/O gates IOG
5
(not shown), . . . , and IOG(
4
m
-3) are connected to the column select signal line CSL
0
. The I/O gate IOG
3
, I/O gates IOG
7
(not shown), . . . , and I/O gate IOG(
4
m
-1) are connected to the column select signal line CSL
1
. The I/O gate IOG
4
, I/O gates IOG
8
(not shown), . . . , and I/O gate IOG(
4
m
) are connected to the column select line CSL
2
. The I/O gate IOG
2
, I/O gates IOG
6
(not shown), . . . , and IOG(
4
m
-2) are connected to t

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