Semiconductor memory device and its test method as well as...

Details Semiconductor memory device and its test method as well as... Semiconductor memory device and its test method as well as...

2006-04-25

2006-04-25

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Read/write circuit

Testing

C365S222000, C365S230030

Reexamination Certificate

active

07035154

ABSTRACT:
The present invention provides a semiconductor memory device capable of checking operation in the worst case in address combinations, and its manufacturing method. Specific data for test are written into a memory cell array30.Then, a test signal TE1is set “1” to set a device in a test mode. Refresh addresses for test are then stored in a data store circuit51.A first address for test is applied to an address terminal21,whereby a normal read or write operation is accomplished based on the first address for test. A second address for test is applied to the address terminal21, whereby a refresh operation is accomplished based on the address for test, and subsequently another normal read or write operation is accomplished based on the second address for test. Data of the memory cell array30are checked to decide the presence or absence of any abnormality.

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