Semiconductor memory device and its test method

Details Semiconductor memory device and its test method Semiconductor memory device and its test method

2006-09-26

2008-11-11

Nguyen, Dang T (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S241000, C365S189080

Reexamination Certificate

active

07450449

ABSTRACT:
A test circuit is connected to a memory core integrated unit of SRAM. When the memory core integrated unit is to be tested, a test start signal is set to a high level so that one of a bit line and an inverted bit line is used for data write and the test circuit sets data to this selected bit line. The other bit line is used for data read, and the written data is set to this bit line in the normal operation. Whether each memory core is not defective is judged by EOR which confirms data set to the bit line and data set to the inverted bit line are mutually inverted each other. A test method is realized which can test a defect of each memory core of a semiconductor memory such as SRAM in a short time.

REFERENCES:
patent: 6181640 (2001-01-01), Kang
patent: 6515922 (2003-02-01), Yamagata
patent: 2005/0063238 (2005-03-01), Nambu et al.
patent: 4344399 (1992-11-01), None
patent: 11066889 (1999-03-01), None
patent: 2001023400 (2001-01-01), None
patent: 2001210095 (2001-08-01), None

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