Semiconductor memory device and its data writing method

Details Semiconductor memory device and its data writing method Semiconductor memory device and its data writing method

2002-09-20

2009-02-24

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S718000

Reexamination Certificate

active

07496810

ABSTRACT:
This invention provides a semiconductor memory device and its data writing method capable of saving the needed time to a minimum even in repeating a data write operation maximum number of times. More specifically, this invention provides a semiconductor memory device and its data writing method as follows. A flash memory101is set at a test mode by fixing the test pad TP at L level. When a verify operation passes, a verify pass signal input terminal (VPASS) of a data write controlling circuit WCC and a verify pass signal input terminal (VPASS) of a data write counter circuit WCT are fixed at L level by a verify pass signal invalidating means3although a verify circuit VC outputs an L level verify pass signal VPASS. A latch circuit LC holds a latched verify pass signal VPL at H level and a verify start signal input terminal (VR) of the verify circuit VC is fixed at L level. A write operation without a verify operation is repeated number of times preset in the data write counter circuit WCT.

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