Semiconductor memory device and information device

Details Semiconductor memory device and information device Semiconductor memory device and information device

2002-06-25

2003-04-15

Lebentritt, Michael S. (Department: 2824)

Static information storage and retrieval

Read/write circuit

With shift register

C365S189020, C365S230020

Reexamination Certificate

active

06549475

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device including a status register for storing various operation states of a memory array capable of data write or erase, and an information device using the same, for example, a computer or an information mobile device.
2. Description of the Related Art
One of semiconductor memory devices capable of storing information even after supply of power is stopped is a flash memory (or a flash EEPROM (Electrically Erasable and Programmable ROM)). The flash memory has a function of electrically erasing data in memory cells in the entire chip or a certain area in the chip (sector or block) in globally. Thus, the flash memory allows the area of a memory cell to be as small as that of an EPROM (Erasable and Programmable ROM).
In such a flash memory (nonvolatile semiconductor memory device), the memory arrays are in a greater number of operation states (for example, write, block erase, global erase of the entire chip, and read of the status register) than in a RAM (Random Access Memory) capable of performing information read and write within a short time period. In conventional EPROM or EEPROM, such a great number of operation states cannot correspond, one to one, to combinations of external control signals (for example, a chip enable signal (/CE), a write enable signal (/WE) and an output enabler signal (/OE)). The reason is that the number of control signals are not sufficient for all the operation states of the memory arrays. Therefore, it is necessary to add new control signals.
However, addition of the new control signal lines results in less ease in use. Therefore, a system of performing controls by commands is mainly used today.
FIG. 9
is a block diagram showing a partial structure of a conventional nonvolatile semiconductor memory device
100
. As shown in
FIG. 9
, the nonvolatile semiconductor memory device
100
includes a memory array
120
, a command state machine (CSM)
102
, a write state machine (WSM)
103
, a row decoder
104
, a column decoder
105
, a block selection circuit
106
, a status register (SR)
107
, block protect setting sections (BPs)
108
, a data switching circuit
109
, a block status register (BSR)
110
, a data bus
112
, an address bus
113
, a reset signal input line
114
, an erase/write voltage generation circuit
115
, and a sense amplifier
116
.
The memory array
120
includes a plurality of erase blocks
101
(erase blocks
1
through n) each including a plurality of memory cells.
The command state machine
102
(hereinafter, referred to as the “CSM
102
”) decodes an input command
111
and transfers the decoding result (for example, block erase or write) to the write state machine
103
. The CSM
102
is connected to, for example, a command input line and a reset signal input line
114
. In synchronization with the command
111
or a reset signal R externally input to the CSM
102
, the input levels of a chip enable signal /CE, a write enable signal/WE, an output enable signal /OE and the like change.
The write state machine
103
(hereinafter, referred to as the WSM
103
) executes various operations (for example, block erase/write) in accordance with the decoding result of the input command
111
. More specifically, when a block which is selected by the block selection circuit
106
(described below) is not in, for example, an erase prohibition state (a block lock state), the WSM
103
can globally erase the data in the block. When the block is in the block lock state, the WSM
103
does not rewrite the data stored in the block.
The row decoder
104
sequentially selects word lines (not shown) in the memory array
120
so as to electrically connect each of the memory cells in each row connected to the selected word line to a corresponding bit line.
The column decoder
105
selects one of a plurality of bit lines (not shown) in the memory array
120
so as to connect the selected bit line to the sense amplifier
116
(described below).
The block selection circuit
106
selects one of the n number of erase blocks
101
.
The status register
107
(hereinafter, referred to as the “SR
107
”) stores the data representing an operation state of the memory array
120
(for example, block erase/write).
The block protect setting sections
108
(hereinafter, referred to as the “BPs
108
”) are each a control bit for locking or unlocking an erase block
101
corresponding thereto. Data indicating whether each erase block
101
is locked or unlocked is stored in the block status register
110
(hereinafter, referred to as the “BSR
110
”) of each erase block
101
as described below.
The data switching circuit
109
selects one of data stored in the memory array
120
, data stored in the SR
107
or data stored in the BSR
110
to be read.
The BSR
110
corresponding to each erase block
101
stores data indicating whether the corresponding erase block
101
is in a locked state or an unlocked state. The BSR
110
also stores data indicating which erase block
101
is selected by an address externally designated.
The command
111
is a command signal as a control instruction which is input by the user. The command
111
instructs execution of various operations (for example, block erase/write).
The data bus
112
has a 16-bit width in order to allow data D to be transferred between the CSM
102
or the data switching circuit
109
and external devices. The data bus
112
is not limited to having a 16-bit width, and may have, for example, a 24-bit or 32-bit width.
The address bus
113
receives an address signal A, and the reset signal line
114
receives a reset signal R.
The erase/write voltage generation circuit
115
is provided for erase or write. The erase/write voltage generation circuit
115
receives a prescribed voltage from an external power supply Vcc, and when necessary, generates a high voltage of about 12 V. For executing a negative gate erase, the erase/write voltage generation circuit
115
generates a negative potential.
The sense amplifier
116
amplifies the bit line voltage selected by the column decoder
105
so as to sense information stored in the selected memory cell.
The nonvolatile semiconductor memory device having the above-described structure operates as follows.
When the user inputs the command
111
, the CSM
102
decodes the command
111
and outputs the decoding result to the WSM
103
. The WSM
103
executes a memory operation in accordance with the command
111
(for example, block erase/write).
For example, a block erase operation is usually performed as follows. First, one of the erase blocks
101
to be erased is selected, and data “0” is written in all the memory cells (not shown) in the selected erase block
101
(i.e., threshold voltage Vth in the memory cell transistor is changed to a HIGH level).
Next, when the threshold voltage Vth of all the memory cells in the selected erase block
101
becomes equal to or higher than a prescribed value, data stored in the memory cells in the erase block
101
is globally erased (i.e., the threshold voltage Vth is changed to a LOW level).
This series of operations are controlled by the WSM
103
, and the result of the operations (for example, the result that the data in the erase block
101
has been erased) is stored in the SR
107
and in the corresponding BSR
110
as data which represents the operation state of the memory array
120
.
In order to read the data stored in the SR
107
and the data stored in the BSR
110
, the conventional flash memory needs to be operated as follows.
While the WSM
103
is executing a command, 8-bit data stored in the SR
107
can be read, not the data stored in the memory array
120
, by changing the chip enable signal /CE and the output enable signal/OE to a LOW (active) level so as to perform a read operation. Even when a 16-bit data bus is used, the data stored in the SR
107
is output to the lower 8 bits and the upper 8 bits are not used, regardless of the designated address.
Data stored in the SR
107
will be described us

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