Semiconductor memory device and fabrication process

Details Semiconductor memory device and fabrication process Semiconductor memory device and fabrication process

1996-07-12

1997-06-17

Clawson, Jr., Joseph E.

Static information storage and retrieval

Systems using particular element

Semiconductive

365149, 365168, 36518506, 36518501, 257324, 257640, G11C 1140

Patent

active

056403453

ABSTRACT:
Provided between a control gate electrode and a channel region of the EEPROM memory cell is a capacitor. Formed on the channel region are a first gate dielectric layer of silicon oxide, a first carrier capture layer of silicon nitride, a carrier migration layer of n.sup.31 polysilicon, a second carrier capture layer of silicon nitride, and a second gate dielectric layer of silicon oxide. The carrier capture state of the carrier capture layer is changed to generate a polarization state in the capacitor, and the generated polarization state is held as data. The gate dielectric layer is not destroyed since the movement of carriers is limited to within the capacitor, and by adjusting the carrier bound energy, low-voltage drive can be accomplished.

REFERENCES:
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patent: 5294819 (1994-03-01), Simko
patent: 5319229 (1994-06-01), Shimoji et al.
patent: 5336936 (1994-08-01), Allen et al.
I.C. Chen, et al., "Oxide breakdown dependence on thickness and hole current", pp. 660-663, 1986 IEDM Proceeds.

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