Semiconductor memory device and fabrication method thereof...

Details Semiconductor memory device and fabrication method thereof... Semiconductor memory device and fabrication method thereof...

2006-04-25

2006-04-25

Trinh, Michael (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S346000, C438S279000, C438S486000

Reexamination Certificate

active

07034368

ABSTRACT:
A semiconductor memory device and fabrication method of same includes the processes of forming sacrifice gates on a silicon substrate with the sacrifice gates apart from each other. A first conductive layer is formed on an exposed portion of the silicon substrate between the sacrifice gates and a first inter-insulation layer is formed that exposes the first conductive layer and the sacrifice gates. The exposed sacrifice gates are removed to form openings and damascene gates are subsequently formed in the openings. Capping layers are formed on the top of the gates and a second conductive layer is formed on the exposed first conductive layer. A second inter-insulation layer is formed on the silicon substrate, and bit line contacts that expose the second conductive layer are formed by etching the second inter-insulation layer.

REFERENCES:
patent: 5631185 (1997-05-01), Kim et al.
patent: 6030894 (2000-02-01), Hada et al.
patent: 6417055 (2002-07-01), Jang et al.
patent: 6515338 (2003-02-01), Inumiya et al.
patent: 10-242411 (1998-09-01), None
English language abstract of the Japanese Publication No. 10-242411.

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