Semiconductor memory device and erase method for memory array

Details Semiconductor memory device and erase method for memory array Semiconductor memory device and erase method for memory array

2005-05-03

2005-05-03

Le, Thong Q. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Erase

C365S148000

Reexamination Certificate

active

06888773

ABSTRACT:
An object of the invention is to provide a nonvolatile semiconductor memory device and an erase method for a memory cell array that have high degree of freedom and that are capable of quickly and securely implementing data erase and reprogramming. In a memory cell array, memory cells each configured of a variable resistor element for storing information through variations in electric resistance and a selected transistor are arranged in a matrix, and word lines (WL1, . . . , WLm) and bit lines (BL1, . . . , BLn) are arranged to select a predetermined memory cell. For the memory cell array, erase means is provided that sets the electric resistance of the variable resistor element to a predetermined erased state by applying voltage under a predetermined application condition to the word line (WL), bit line (BL), and source line (SL). The erase means switches between a batch-erase mode and an individual-erase mode. The batch-erase mode is used to perform batch erase of all the memory cells in the memory cell array, and the individual-erase mode is used to perform individual erase of a part of the memory cells in the memory cell array.

REFERENCES:
patent: 5831905 (1998-11-01), Hirano
patent: 6542410 (2003-04-01), Hirano
patent: 9-320282 (1997-12-01), None

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