Semiconductor memory device and electronic information...

Details Semiconductor memory device and electronic information... Semiconductor memory device and electronic information...

2003-01-31

2004-12-14

Le, Thong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S218000, C365S189011

Reexamination Certificate

active

06831869

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device used for an electronic information device such as, for example, a cellular phone, and in particular to a nonvolatile semiconductor memory device such as, for example, a flash EEPROM. The present invention also relates to an electronic information device using such a semiconductor memory device.
2. Description of the Related Art
In one type of conventional semiconductor memory device, a non-redundant, regular memory cell is accessed based on an input address signal, and when a regular word line used for accessing the regular memory cell is defective, a redundant word line is used instead of the regular word line so as to access a redundant memory cell.
With reference to
FIGS. 4 through 6
, such a conventional semiconductor memory device will be described.
FIG. 4
is a block diagram illustrating a partial structure of a conventional semiconductor memory device
100
. More specifically,
FIG. 4
shows a partial structure of a control system for selecting a regular word line and a redundant word line.
As shown in
FIG. 4
, the semiconductor memory device
100
includes an address redundancy determination circuit CAJD, a regular and redundant word line control circuit CXDEC
1
, a plurality of regular memory cell arrays MRG, a plurality of redundant memory cell arrays MRD, a plurality of regular word line drivers CDRV, and a plurality of redundant word line drivers CRDRV
1
.
The address redundancy determination circuit CAJD determines whether an input address signal SAD (externally input) and a defective address signal SBAD match each other and outputs an address redundancy match signal SAM as an output determination signal (for example, a defective word line determination signal) which represents the determination result for each address. When the input address signal SAD and the defective address signal SBAD match each other, the level of the address redundancy match signal SAM is HIGH. When the input address signal SAD and the defective address signal SBAD do not match each other, the level of the address redundancy match signal SAM is LOW.
The regular and redundant word line control circuit CXDEC
1
outputs a redundant word line selection signal SRED when the address redundancy match signal SAM is at the HIGH level, and outputs a regular word line selection signal SREG when the address redundancy match signal SAM is at the LOW level.
The semiconductor memory device
100
includes a plurality of memory cell array areas referred to as memory blocks. Each memory cell array area includes a plurality of regular memory cell arrays MRG and a plurality of redundant memory cell arrays MRD. Each regular memory cell array MRG includes a plurality of memory cells, and each redundant memory cell array MRD includes a plurality of memory cells. Memory operations including data write to a plurality of prescribed memory cells corresponding to an input address signal SAD and data read and erase from the plurality of memory cells can be performed.
Each memory cell array area includes one regular word line driver CDRV and one redundant word line driver CRDRV
1
. In order to perform the above-described memory operations, each regular word line driver CDRV selects a regular word line corresponding to the input address signal SAD, or each redundant word line driver CRDRV
1
selects a redundant word line corresponding to the input address-signal SAD.
With the above-described structure, an input address signal SAD having a plurality of bits is input to the address redundancy determination circuit CAJD and also to the regular and redundant word line control circuit CXDEC
1
.
The address redundancy determination circuit CAJD receives a defective address signal SBAD as well as the input address signal SAD, and determines whether the input address signal SAD matches the defective address signal SBAD or not.
As described above, when the input address signal SAD and the defective address signal SBAD match each other, the level of the address redundancy match signal SAM (as a determination signal regarding each input address signal SAD) is HIGH. When the input address signal SAD and the defective address signal SBAD do not match each other, the level of the address redundancy match signal SAM is LOW. The address redundancy match signal SAM is output from the address redundancy determination circuit CAJD to the regular and redundant word line control circuit CXDEC
1
.
When the address redundancy match signal SAM is at the HIGH level, the regular and redundant word line control circuit CXDEC
1
outputs a redundant word line selection signal SRED to one of the redundant word line drivers CRDRV
1
. When the address redundancy match signal SAM is at the LOW level, the regular and redundant word line control circuit CXDEC
1
outputs a regular word line selection signal SREG to one of the regular word line drivers CDRV.
Based on the word line selection signal, the regular word line driver CDRV or the redundant word line driver CRDRV
1
corresponding to a selected memory block (memory block selection signal SBLK is HIGH) is activated, and a desired regular memory cell array MRG or a desired redundant memory cell array MRD is selected. This selection is performed by raising the potential of a regular word line WLREG corresponding to the desired regular memory cell array MRG or the potential of a redundant word line WLRED corresponding to the desired redundant memory cell array MRD. In this manner, memory operations including data write to, data read from, or data erase from a memory cell corresponding to the input address signal SAD are performed.
FIG. 5
is a block diagram illustrating a partial structure of conventional regular and redundant word line selection circuits including the regular and redundant word line control circuit CXDEC
1
.
As shown in
FIG. 5
, the regular and redundant word line control circuit CXDEC
1
includes a comprehensive redundancy determination circuit CJD, an erase processing circuit CER, a forcible redundant word line selection control circuit CAR, and a regular word line predecoder CPD
1
. A redundant word line selection circuit CXRED
1
includes the comprehensive redundancy determination circuit CJD, the erase processing circuit CER, the forcible redundant word line selection control circuit CAR, and the redundant word line driver CRDRV
1
. A regular word line selection circuit CXREG
1
includes the regular word line predecoder CPD
1
and a regular word line driver CDRV.
The comprehensive redundancy determination circuit CJD comprehensively determines whether each address is redundant or not based on the address redundancy match signal SAM and the input address signal SAD. Then, the comprehensive redundancy determination circuit CJD supplies an output signal SP
1
.
The erase processing circuit CER receives the output signal SP
1
and an erase processing signal SER which instructs execution of special processing when data is erased from a memory cell. Based on these signals, the erase processing circuit CER executes the special processing at the time of data erase. Then, the erase processing circuit CER outputs a defective word line selection control signal S
2
R to the regular word line predecoder CPD
1
, and supplies an output signal SP
2
to the forcible redundant word line selection control circuit CAR.
The special processing at the time of data erase performed by the erase processing circuit CER will be briefly described with a nonvolatile semiconductor memory device, more specifically, a flash EEPROM, used as an example.
In a flash EEPROM referred to as an NOR, a plurality of memory cells are connected to one bit line. Data stored in the memory cells is generally erased in units of a memory block which includes a plurality of memory cells. Data erase is specifically performed as follows.
Before erasing data, data write is performed to all the memory cells in the memory block which is the target of data erase. (This data write operation will be referred to as “prepr

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