Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2005-08-02
2005-08-02
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S149000
Reexamination Certificate
active
06925023
ABSTRACT:
In the semiconductor memory device of the invention, while a write enable signal supplied from an external device is at an active level representing a data writing request, an access control module prohibits start of any of a read access operation, a write access operation, and a refresh operation, even in the case of generation of any one of a read access request, a write access request, and a refresh request. Even in the case of generation of a write access request or a refresh request in advance, the access control module preferentially executes a read access operation in response to a read access request generated by a change of an external access timing signal to an inactive level while the write enable signal is at an inactive level. This arrangement desirably eliminates the long rate restriction of the semiconductor memory device.
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Mizugaki Koichi
Otsuka Eitaro
Le Vu A.
Oliff & Berridg,e PLC
Seiko Epson Corporation
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