Semiconductor memory device and electronic apparatus

Details Semiconductor memory device and electronic apparatus Semiconductor memory device and electronic apparatus

2006-09-14

2008-12-09

Nguyen, Dang T (Department: 2824)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S149000, C365S214000

Reexamination Certificate

active

07463505

ABSTRACT:
A semiconductor memory device having: a memory cell array with m memory cells arranged in a first direction and n memory cells arranged in a second direction in a grid, each memory cell having a capacitor part using a ferroelectric film, and also having a first terminal, a second terminal, and a third terminal; two or more first wirings connecting the first terminals of the m memory cells arranged in the first direction; two or more second wirings connecting the second terminals of the n memory cells arranged in the second direction; two or more third wirings connecting the third terminals of the m memory cells, and means for selecting a third wiring from among the third wirings, the third wiring being selected based on the result of calculation in an adder circuit and a subtractor circuit.

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Shoichiro Kawashima, Bitline GND Sensing Technique for Low-Voltage Operation FeRAM, IEEE Journal of Solid-State Circuits, IEEE Service Center, Piscataway, NJ, US, vol. 37, No. 5, May 2002, pp. 592-598.
IEEE Journal of Solid-State Circuits, vol. 37, No. 5, May 2002 p. 592-598 “Bitline GND Sensing Technique for Low-Voltage Operation FeRAM”.

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