Semiconductor memory device and electronic apparatus

Static information storage and retrieval – Systems using particular element – Ferroelectric

Reexamination Certificate

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C365S210130, C365S230030

Reexamination Certificate

active

07995370

ABSTRACT:
A ferroelectric memory includes a memory cell array including a first unit block, a second unit block, and a plurality of dummy cells. The plurality of dummy cells being arranged toward a column direction and being disposed between the first unit block and the second unit block. The first unit block including a plurality of first memory cells arranging in t rows, and including a plurality of first plate lines arranging toward a row direction. The second unit block including a plurality of second memory cells arranged in t rows, and including a plurality of second plate lines arranging toward a row direction. Each of the plurality of dummy cells including a ferroelectric capacitor. Either of the first second plate line or the second plate line of the second unit block extending above the plurality of dummy cells.

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IEEE Journal of Solid-State Circuits, vol. 37, No. 5, May 2002, p. 592-598 “Bitline GND Sensing Technique for Low-Voltage Operation FeRAM”.
Communication from European Patent Office regarding counterpart application.
Shoichiro Kawashima, Bitline GND Sensing Technique for Low-Voltage Operation FeRAM, IEEE Journal of Solid-State Circuits, IEEE Service Center, Piscataway, NJ, US vol. 37, No. 5, May 2002, pp. 592-598.

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