Semiconductor memory device and driving signal generator...

Details Semiconductor memory device and driving signal generator... Semiconductor memory device and driving signal generator...

2000-03-13

2001-05-29

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S189050, C365S230080

Reexamination Certificate

active

06240039

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device where power consumption is lowered by reducing the number of memory cells which are sensed by a sense amplifier.
2. Description of the Related Art
Dynamic random access memories (DRAM) are generally classified dependant upon their operation protocols. For example, a DRAM employing a mode of strobing addresses based upon row address strobe (RASB) signals and column address strobe (CASB) signals is commonly classified as an extended data output DRAM (EDO DRAM). A DRAM employing a mode of strobing commands, addresses, and data based upon clock signals may be classified as a synchronous DRAM. Yet another may be classified as a Rambus DRAM, which employs a mode of strobing commands, addresses and, data in the format of packets based upon clock signals (hereinafter, called a packet protocol mode).
The former two types of DRAMs adopt an address multiplex mode in which the row and column addresses are input through the same pin at predetermined intervals (tRCDmin). On the other hand, the Rambus type DRAM which employs the packet protocol mode may adopt a mode in which the row address and the column address are simultaneously input at a predetermined time, or they are input for a period of time shorter than the tRCDmin. The tRCDmin for DRAM may vary from chip to chip. Here, tRCDmin indicates a time interval for ensuring that a word-line specified by the row address is activated. The tRCDmin time interval also ensures that the bit-line sensing, and read and write operations are performed according to the column address. The packet protocol mode is similar to an address non-multiplex mode in a static RAM (SRAM). In an address non-multiplex mode the row and column addresses may be simultaneously input through different pins.
DRAM operates in either a normal operation mode or a refresh operation mode. The normal operation mode is divided into an operation that selects memory cells and an operation that determines whether read or write will be performed while controlling the input and output of data for selected cells. The operation for selecting a memory cell includes several steps. The operation decodes a row address and selects a corresponding word-line. The operation senses and amplifies bit-lines connected to the selected word-line using sense amplifiers. The operation decodes a column address and selects a corresponding bit-line to provide an output through an input/output line. Finally, the memory cell which is connected to the word-line selected by the row address, and to the bit-line selected by the column address, is selected.
The refresh operation is automatically and periodically performed while generating an internal address which successively changes. The refresh operation is divided into an operation for selecting word-lines, and an operation for sensing and amplifying bit-lines connected to selected word-lines. The word-lines are selected by using sense amplifiers to restore the charge of the memory cells. The operation for selecting a corresponding word-line in the refresh operation is the same as that in the normal operation, with the exception that the internally generated address is used in the refresh operation.
In other words, operations associated with a row address (i.e., the decoding of the row address, the activation of a selected word-line, and the sensing of all bit-lines connected to the selected word-line) in the normal operation mode are essentially the same as those in the refresh operation mode. The difference between the two operation modes is that the normal operation mode uses an external address, and the refresh operation mode uses an internal address.
FIG. 1
is provided to show the concept of word-line selection performed in EDO DRAM.
FIG. 2
is provided to show the concept of word-line selection performed in synchronous DRAM.
The following description referring to
FIGS. 1 and 2
concerning the number of word-lines and memory cells activated in each normal operation mode of EDO DRAM and synchronous DRAM, respectively. During the normal operation, once a command for controlling the operations associated with a row and a row address are input, as shown in
FIG. 1
, the word-lines W/L represented by solid lines are activated in EDO DRAM for 8K refresh. Similarly, the word-lines W/L represented by both solid lines and doted lines are activated in EDO DRAM for 4K refresh. While, as shown in
FIG. 2
, the word-lines W/L represented by solid lines are activated in a bank in synchronous DRAM for 4K refresh. Accordingly, a sensing operation may be performed with respect to the following during the normal operation: a 8K memory cell in EDO DRAM in 8K refresh; a 16K memory cell in EDO DRAM in 4K refresh; and a 4K memory cell (in case where only one bank is selected) in synchronous DRAM in 4K refresh.
Read and write are actually performed with respect to only 4~32 cells among the sensed 8K cells. The locations of memory cells to be read from, and written to, cannot be recognized until a column address is applied.
In the case of a DRAM which employs the address multiplex mode, such as EDO DRAM, or synchronous DRAM, to ensure the completion of the operations associated with a row, a column address must be input after a predetermined period of time (tRCDmin) has passed from the time a row address is input. Consequently, during the normal operation of DRAM in address multiplex mode, the sensing operation should be continuous with respect to all memory cells connected to activated word-lines W/L, until the column address is applied. Even though only a very small number of the 8K cells (in case of 64M) are to be used. Such a continuous sensing operation consumes a large amount of sensing current.
The following description referring to
FIGS. 1 and 2
concerns the numbers of word-lines W/L and memory cells activated in each refresh operation of EDO DRAM and synchronous DRAM. During the refresh operation, once an internal address is input, as shown in
FIG. 1
, word-lines W/L represented by solid lines are activated in EDO DRAM for 8K refresh, and word-lines W/L represented by both solid lines and doted lines are activated in EDO DRAM for 4K refresh. As shown in
FIG. 2
, word-lines W/L represented by both solid lines and doted lines are activated in synchronous DRAM for 4K refresh. Accordingly, a sensing operation is performed with respect to the following during the refresh operation: a 8K memory cell in EDO DRAM in 8K refresh; a 16K memory cell in EDO DRAM in 4K refresh; and a 16K memory cell in synchronous DRAM in 4K refresh.
In DRAM employing the address multiplex mode, EDO DRAM and synchronous DRAM, the same number of word-lines are activated in the normal operation as in the refresh operation when all banks are activated.
Therefore, it may be desirable to have a DRAM which employs the address non-multiplex mode or a DRAM which employs the packet protocol mode which does not need to sense memory cells that will not be used during the normal operation because row and column addresses are input simultaneously or for a period of time shorter than tRCDmin. Accordingly, in semiconductor memory devices employing the address non-multiplex mode or the packet protocol mode and the like, where row and column addresses are input for a period of time shorter than tRCDmin, if the sensing operation is performed for those memory cells selected by the column address, consumption of the current may be reduced.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory device in which, during a normal operation only some memory cells are sensed among memory cells connected to a selected word-line, the row and column addresses being input for a period of time shorter than a RAS to CAS delay time (tRCDmin), thereby reducing power consumption.
It is another object of the present invention to provide a driving signal generator suitable for the above semiconductor memory dev

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