Semiconductor memory device and driving method thereof

Details Semiconductor memory device and driving method thereof Semiconductor memory device and driving method thereof

2009-01-13

2010-11-23

Yoha, Connie C (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S189110, C365S203000, C365S230060

Reexamination Certificate

active

07839711

ABSTRACT:
A memory including; cells, wherein a refresh operation includes a first refresh and a second refresh, in the first refresh, a first potential higher than a gate potential in a retention is applied to the gate in a state having a source potential applied to the drain, and thereafter the gate potential in the retention is applied to the gate, thereby a first current passes to the cell, and in the second refresh, a second potential higher than a gate potential in the retention is applied to the gate, and a third potential higher than the gate potential in the retention is applied to the drain, thereby a second current passes to the cell, and a state of the cell is shifted to an equilibrium state in which amounts of the first and the second currents flowing during one cycle becomes substantially equal.

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Guido Groeseneken, et al., “A Reliable Approach to Charge-Pumping Measurements in MOS Transistors”, IEEE Transactions on Electron Devices, vol. ED-31, No. 1, Jan. 1984, pp. 42-53.
P. Fazan, et al., “A New Block Refresh Concept for SOI Floating Body Memories”, IEEE International SOI Conference, 2003, pp. 15 and 16.

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