Semiconductor memory device and drive method therefor

Details Semiconductor memory device and drive method therefor Semiconductor memory device and drive method therefor

2003-03-21

2004-03-16

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S063000, C365S230010

Reexamination Certificate

active

06707704

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device having memory cells arranged in a matrix, in which each of the memory cells includes a ferroelectric capacitor for storing binary data using displacement of polarization of a ferroelectric film and a selection transistor for selecting the ferroelectric capacitor for data read/write, and a drive method for such a semiconductor memory device.
A conventional semiconductor memory device having memory cells each including a ferroelectric capacitor and a selection transistor arranged in a matrix will be described with reference to FIG.
9
.
FIG. 9
shows four memory cells MC
00
, MC
01
, MC
10
and MC
11
, for example, arranged in a matrix of two rows and two columns. This conventional semiconductor memory device has a 2T2C structure, in which the memory cell MC
00
, for example, includes two ferroelectric capacitors C
0
and C
1
and two selection transistors Q
0
and Q
1
. One of paired electrodes of each of the ferroelectric capacitors C
0
and C
1
is connected to the drain of the corresponding selection transistor Q
0
or Q
1
.
Bit lines BL
0
and XBL
0
constitute a bit line pair, and bit lines BL
1
and XBL
1
constitute another bit line pair. The bit lines BL
0
and XBL
0
are connected to the sources of the corresponding selection transistors Q
0
and Q
1
, respectively.
Word lines WL
0
and WL
1
are connected to the gates of the selection transistors of the memory cells arranged in the word line direction.
Cell plate lines CP
0
and CP
1
are connected to the other electrode of each of the ferroelectric capacitors of the memory cells arranged in the word line direction.
A sense amplifier SA
0
is connected to the bit line pair BL
0
and XBL
0
and also connected to a pair of data bus lines DL
0
and XDL
0
. A sense amplifier SA
1
is connected to the bit line pair BL
1
and XBL
1
and also connected to a pair of data bus lines DL
1
and XDL
1
.
Data write/read operation of the semiconductor memory device shown in
FIG. 9
will be described. Assume that data is to be written in and read from the memory cell MC
00
, as an example.
Data write operation is achieved by writing complementary data in the two ferroelectric capacitors of the memory cell in which the data is to be written. A high voltage is applied to the word line WL
0
to turn on the selection transistors Q
0
and Q
1
, and then voltages of the opposite polarities are applied between the cell plate line CP
0
and the bit line BL
0
and between the cell plate line CP
0
and the bit line XBL
0
. For example, when data “1” is to be written, a high signal is applied to the data bus line DL
0
so that the ferroelectric capacitor C
0
has downward polarization, and a low signal is applied to the data bus line XDL
0
so that the ferroelectric capacitor C
1
has upward polarization. When data “0” is to be written, a low signal is applied to the data bus line DL
0
so that the ferroelectric capacitor C
0
has upward polarization, and a high signal is applied to the data bus line XDL
0
so that the ferroelectric capacitor C
1
has downward polarization.
Data read operation is performed in the following manner.
First, the bit lines BL
0
, XBL
0
, BL
1
and XBL
1
are precharged to a low level. Thereafter, a high voltage is applied to the word line WL
0
to turn on the selection transistors Q
0
and Q
1
, and then a high voltage is applied to the cell plate line CP
0
. By this application, a minute voltage difference occurs between the bit line pair BL
0
and XBL
0
, which is amplified by the sense amplifier SA
0
and output to the data bus pair DL
0
and XDL
0
.
The read operation described above uses the fact that the capacitance value of a ferroelectric capacitor changes with the polarization value previously stored in the ferroelectric capacitor. More specifically, in the case that downward polarization has been written in the ferroelectric capacitor in the data write process, charge is generated with reversal of the polarization when a voltage is applied to the cell plate line CP
0
, and this increases the capacitance value. On the contrary, in the case that upward polarization has been written in the ferroelectric capacitor, no reversal of polarization occurs when a voltage is applied to the cell plate line CP
0
, and this decreases the capacitance value.
The bit line voltage during the read operation is determined by capacitance splitting between the capacitance of the bit line and the capacitance of the ferroelectric capacitor. Therefore, the bit line voltage is high when the ferroelectric capacitor has downward polarization, and it is low when the ferroelectric capacitor has upward polarization. When a high voltage is output from the data bus line DL
0
and a low voltage is output from the data bus line XDL
0
after amplification of the voltages of the bit line pair, this indicates that the ferroelectric capacitor CO has downward polarization and the ferroelectric capacitor C
1
has upward polarization. Therefore, It can be decided that the stored data is “1”. Contrarily, when a low voltage is output from the data bus line DL
0
and a high voltage is output from the data bus line XDL
0
, it can be decided that the stored data is “0”.
In the conventional semiconductor memory device, when data is read from the ferroelectric capacitor, the polarization of the ferroelectric capacitor is reversed. In other words, the data is corrupted. It is therefore necessary to rewrite the data after the read operation. The data read operation is only completed by performing rewrite of the data after the output of the data to the data bus.
If the polarization of the ferroelectric film of the ferroelectric capacitor is repeatedly reversed, the ferroelectric film becomes fatigued and degraded, causing reduction in polarization value. Therefore, the life of the ferroelectric capacitor will end after about 10 billion times of polarization reversal.
In the conventional semiconductor memory device, polarization reversal is necessary during the data read operation, in addition to during the data write operation. Therefore, the number of times of data rewrite and the number of times of data read are limited to about 10 billion in total.
In view of the above problem, the inventors of the present invention proposed a semiconductor memory device that permits increase of the number of times of read, that is, a semiconductor memory device in which data is not corrupted after the data read operation.
The semiconductor memory device having the above feature will be described with reference to FIG.
10
.
FIG. 10
shows two memory cell blocks MC
0
and MC
1
, for example, arranged in the word line direction. Each of the memory cell blocks MC
0
and MC
1
has four memory cells, for example, arranged in the bit line direction. The four memory cells constituting the memory cell block MC
0
, for example, include ferroelectric capacitors C
0
, C
1
, C
2
and C
3
and selection transistors Q
0
, Q
1
, Q
2
and Q
3
respectively connected in series. The memory cell block MC
0
has a block selection transistor Q
4
connected to one of common nodes, and a write transistor Q
5
and a read transistor Q
6
connected to the other common node. The memory cell block MC
1
has a block selection transistor XQ
4
connected to one of common nodes, and a write transistor XQ
5
and a read transistor XQ
6
connected to the other common node.
The operation of writing/reading data in/from the semiconductor memory device having the configuration described above will be described. Assume that complementary data is to be written in and read from the ferroelectric capacitors C
2
and XC
2
, as an example.
The data write operation is performed in the following manner.
A high signal is applied to a block selection line BS, a write transistor control line RE and a selected word line WL
2
, to turn on the block selection transistors Q
4
and XQ
4
, the write transistors Q
5
and XQ
5
and the cell selection transistors Q
2
and XQ
2
. Contrarily, a low signal is applied to non-selected word l

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