Semiconductor memory device and defective memory cell correction

Details Semiconductor memory device and defective memory cell correction Semiconductor memory device and defective memory cell correction

1993-06-18

1996-08-27

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular signal path connections

257529, 365200, 371 102, H01L 310328, H01L 310336, H01L 31072, H01L 31109

Patent

active

055503942

ABSTRACT:
To provide a semiconductor memory device characterized by the fact that it can prevent errors in the redundant memory address coincidence signal generating circuit caused by the intrinsic resistance of the fuse in the fuse decoder, and it has a redundant mechanism for generating the high-speed address coincidence signal. It has multiple logic gate means and fuses programmable by the gate output. The output signal of each fuse is wired to generate address coincidence signal.

REFERENCES:
patent: 4989181 (1991-01-01), Harada
patent: 5117388 (1992-05-01), Nakano et al.
patent: 5122987 (1992-06-01), Kihara
patent: 5179536 (1993-01-01), Kasa et al.

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