Semiconductor memory device and data transferring structure and

Details Semiconductor memory device and data transferring structure and Semiconductor memory device and data transferring structure and

1994-01-31

1999-04-13

Lane, Jack A.

Static information storage and retrieval

Read/write circuit

For complementary information

36518905, 365194, 365207, 365233, G11C 706

Patent

active

058944400

ABSTRACT:
Each of divided bit line pairs is selectively connected to a sub-input/output line pair through transfer gates. A register is connected to the sub-input/output line pair. Data is transferred through the sub-input/output line pair between the register and a selected bit line pair. A sense amplifier is connected to each of the bit line pairs. Sense amplifiers are independently driven by separate sense amplifier activating signals. Therefore, even if data is transferred to the selected bit line pair from the register, fluctuations in potential on the bit line pair caused in such a case does not affect a sense amplifier activating signal connected to a non-selected bit line pair. As a result, data stored in the non-selected memory cell is prevented from being destroyed.

REFERENCES:
patent: 4330852 (1982-05-01), Redwine et al.
patent: 4498155 (1985-02-01), Rao
patent: 4541075 (1985-09-01), Dill et al.
patent: 4590588 (1986-05-01), Ihoh et al.
patent: 4675845 (1987-06-01), Itoh et al.
patent: 4757473 (1988-07-01), Kurihara et al.
patent: 4757477 (1988-07-01), Nagayama et al.
patent: 4758987 (1988-07-01), Sakui
patent: 4777625 (1988-10-01), Sakui et al.
patent: 4791616 (1988-12-01), Taguchi et al.
patent: 4819207 (1989-04-01), Sakui et al.
patent: 4825411 (1989-04-01), Hamano
patent: 4839868 (1989-06-01), Sato et al.
patent: 4855959 (1989-08-01), Kobayashi
patent: 4879692 (1989-11-01), Tokushige
patent: 4891795 (1990-01-01), Pinkham et al.
patent: 4899310 (1990-02-01), Baba et al.
patent: 4912678 (1990-03-01), Mashiko
patent: 4914630 (1990-04-01), Fujishima et al.
patent: 4916671 (1990-04-01), Ichiguchi
patent: 4931994 (1990-06-01), Matsui et al.
patent: 4933907 (1990-06-01), Kumanoya et al.
patent: 4937788 (1990-06-01), Harada
patent: 4941129 (1990-07-01), Oshima et al.
patent: 4970685 (1990-11-01), Koyanagi
Nikkei Electronics 1985 (pp. 211-240).
"A CMOS Dual Port Memory with Serial Read/Write Function for Graphic Systems", K. Mashiko et al., pp. 636-643, IEEE Transactions on Consumer Electronics, vol. CE-32, No. 3, Aug. 1986.
Pinkham et al, "A High Speed Dual Port Memory with Simultaneous Serial and Random Mode Access for Video Applications", IEEE Journal of Solid-State Circuits, vol. SC-19, No. 6 (Dec. 1984) pp. 999-1007.

Affiliated with

Also associated with

Rating

Semiconductor memory device and data transferring structure and does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device and data transferring structure and , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device and data transferring structure and will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-226184