Semiconductor memory device and data read method thereof

Details Semiconductor memory device and data read method thereof Semiconductor memory device and data read method thereof

2001-11-09

2003-09-02

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S189011, C365S230060

Reexamination Certificate

active

06614710

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of Korean Patent Application No. 2000-69234, filed on Nov. 21, 2000, the disclosures of which are incorporated by reference herein in their entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention refers to a semiconductor memory device and, more particularly, to a read bitline arrangement comprising multi data read/write ports. In addition, a data read method utilizing the device is also described.
2. Description of Related Art
In general, a pair of bitlines connected to a cell of memory cell array in a semiconductor memory device reads data in reading operations and writes data in writing operations. Therefore, because the semiconductor memory device cannot perform both data reading and data writing operations simultaneously, the typical semiconductor memory device comprises unique data read/write ports in transmitting data.
On the other hand, memory devices having multiple data read and write ports provide separate read bitlines and write bitlines to read and write data and thereby permit read and write operations to be performed independently.
FIG. 1
is a block diagram illustrating an example of a conventional semiconductor memory device with multiple read ports and write ports.
The conventional semiconductor memory device of
FIG. 1
includes memory cell array
10
, first and second row read address decoders
12
-
1
and
12
-
2
, first and second row write address decoders
14
-
1
and
14
-
2
, first and second column read multiplexers
16
-
1
and
16
-
2
, first and second column write multiplexers
18
-
1
and
18
-
2
, and first and second column read address decoders
20
-
1
and
20
-
2
. Further, the conventional semiconductor memory device of
FIG. 1
also includes first and second column write address decoders
22
-
1
and
22
-
2
, first and second write drivers
24
-
1
and
24
-
2
, first and second data input buffers
26
-
1
, and
26
-
2
, and first and second data output buffers
28
-
1
and
28
-
2
.
In
FIG. 1
, the memory cell array
10
comprises (1) multiple pairs of read bitlines rb
11
and rb
12
, rb
21
and rb
22
, . . . , rbk
1
and rbk
2
, (2) multiple pairs of read word lines RWL
11
and RWL
12
, RWL
21
and RWL
22
, . . . , RWLm
1
and RWLm
2
, (3) multiple pairs of write bitlines wb
11
and wb
12
, wb
21
and wb
22
, . . . , wbk
1
and wbk
2
, (4) multiple pairs of write word lines WWL
11
and WWL
12
, WWL
21
and WWL
22
, . . . , WWLm
1
and WWLm
2
, and a plurality of memory cells MC connected to those corresponding four types of pairs of lines.
In response to both signals applied from write word lines WWL
11
, WWL
21
, . . . , WWWm
1
, and write control signals wc
11
, wc
21
, . . . , wck
1
, each of a plurality of memory cells MC store data from each of corresponding write bitlines wb
11
, wb
21
, . . . , wbk
1
. In a similar way, in response to both signals applied from write word lines WWL
12
, WWL
22
, . . . , WWWm
2
, and write control signals wc
12
, wc
22
, . . . , wck
2
, each of the memory cells MC store data from each of corresponding write bitlines wb
12
, wb
22
, . . . , wbk
2
. Even though not illustrated in
FIG. 1
, write control signals wc
11
, wc
21
, . . . , wck
1
are generated by buffering and delaying first column-selecting control signals WY
11
, WY
12
, . . . , WY
18
. Write control signals wc
12
, wc
22
, . . . , wck
2
are generated by buffering and delaying second column-selecting control signals WY
21
, WY
22
, . . . , WY
28
.
The device of
FIG. 1
includes two data read ports and two data write ports.
The functions of the blocks in the semiconductor memory device of
FIG. 1
are as follows:
The first row read address decoder
12
-
1
decodes a first row read address FRRA, and selects one of first read word lines RWL
11
, RWL
21
, . . . , RWLm
1
. The second row read address decoder
12
-
2
decodes a second row read address SRRA and selects one of second read word lines RWL
21
, RWL
22
, . . . , RWLm
2
. The first row write address decoder
14
-
1
decodes a first row write address FRWA and selects one of first write word lines WWL
11
, WWL
21
, . . . , WWLm
1
. The second row write address decoder
14
-
2
decodes a second row write address SRWA and selects one of second write word lines WWL
21
, WWL
22
, . . . , WWLm
2
. The first column read multiplexer
16
-
1
selectively outputs data through read bitlines rb
11
, rb
21
, . . . , rbm
1
. In this case, when a multiplexer is a two-input type, the multiplexer selects a read data transmitted from a selected line between two adjacent read bitlines and outputs the selected read data. In a similar way, the multiplexer of a four-input type selects a read data transmitted from a selected line among four adjacent read bitlines and outputs the selected read data. Therefore, the multiplexer of an eight-input type selects a read data transmitted from a selected line among eight adjacent read bitlines and outputs the selected read data.
FIG. 1
illustrates a semiconductor memory device with an eight-input multiplexer, meaning that, in response to the column-selecting control signals RY
11
, RY
12
, . . . , RY
18
, the multiplexer of the eight-input type selects a read data transmitted from a selected line among eight adjacent read bitlines and outputs the selected read data. The second column read multiplexer
16
-
2
outputs a read data selectively according to the input type of the multiplexer in the same way as the first column read multiplexer
16
-
1
selectively.
The first column write multiplexer
18
-
1
puts data to write bitlines wb
11
, wb
21
, . . . , wbm
1
and the second column write multiplexer
18
-
2
puts data to write bitlines wb
12
, wb
22
, . . . , wbm
2
. In response to column-selecting control signals WY
11
, WY
12
, . . . WY
18
and WY
21
, WY
22
, . . . , WY
28
, the first and the second column write multiplexers
18
-
1
and
18
-
2
apply the data to a selected one line of a bitline pair in a manner analogous to the read operations of the first and the second column read multiplexers
16
-
1
and
16
-
2
.
The first column read address decoder
20
-
1
decodes three bits of the first column read address FCRA and generates eight column-selecting control signals RY
11
, RY
12
, . . . , RY
18
. The second column read address decoder
20
-
2
decodes three bits of the second column read address SCRA and generates eight column-selecting control signals RY
21
, RY
22
, . . . , RY
28
. The first column write address decoder
22
-
1
decodes three bits of the first column write address FCWA and generates eight column-selecting control signals WY
11
, WY
12
, . . . , WY
18
. The second column write address decoder
22
-
2
decodes three bits of the second column write address SCWA and generates eight column-selecting control signals WY
21
, WY
22
, . . . , WY
28
.
The first write driver
24
-
1
drives the first write data and the second write driver
24
-
2
drives the second write data through the write multiplexers. The first data input buffer
26
-
1
buffers first input data Din
1
from the outside and generates a first write data. The second data input buffer
26
-
2
buffers second input data Din
2
and generates a second write data. The first data output buffer
28
-
1
buffers first read data from the first column read multiplexer
16
-
1
and generates a first output data Dout
1
. The second data output buffer
28
-
2
buffers second read data from the second column read multiplexer
16
-
2
and generates a second output data Dout
2
.
Operations of the semiconductor memory device of
FIG. 1
are as follows:
An applied write enable signal (not shown) enables a write operation and then the write operation is executed when a first write address and a first input data are applied on the rising edge of a clock signal.
An example of a write operation may be illustrated with the assumption that the first input data Din
1
is “00 . . . 0”, the first row write address FRWA is “00 . . . 0”, and the first column write address FCWA is “000”.
The first data

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