Semiconductor memory device and data read method thereof

Details Semiconductor memory device and data read method thereof Semiconductor memory device and data read method thereof

2000-07-17

2001-09-25

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S189050, C365S205000, C365S063000

Reexamination Certificate

active

06295244

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device and a data read method thereof whose data read speed can be improved in the case of its read operation.
DISCUSSION OF RELATED ART
The data read circuit in a conventional semiconductor memory device consists of a sense amplifier, a main buffer, a dynamic/static converter and a data output buffer. Therefore, in a data read operation, the conventional semiconductor device outputs data output from memory cell array blocks, through the sense amplifier, main buffer, dynamic/static converter and data output buffer. That is, the conventional semiconductor memory device includes the dynamic/static converter disposed between the main buffer and data output buffer, to convert dynamic data output from the main buffer into static data, and then to send it to the data output buffer. This allows the data output buffer to stably latch the data according to a data output buffer control signal KPIPE. However, the conventional semiconductor memory device has a longer data read path because it comprises the dynamic/static converter, delaying its data read speed.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a semiconductor memory device and a data read method thereof that substantially overcomes one or more of the problems characterizing the prior art.
An object of the present invention is to provide a semiconductor memory device whose data read speed can be improved in the case of a data read operation.
Another object of the present invention is to provide a data read method of a semiconductor memory device whose data read speed can be improved in the case of a data read operation.
To accomplish the object of the present invention, there is provided a semiconductor memory device which comprises: a plurality of memory cell array blocks; a predetermined number of main buffers for resetting a predetermined number of pair of main data lines corresponding to a predetermined number of pairs of data output from each of the plurality of memory cell array blocks in response to a main buffer control signal, and for generating a predetermined number of pairs of data having complementary levels when the data of each of the predetermined number of pairs of main data lines reach complementary levels, the predetermined number of pairs of data items being reset after a lapse of a predetermined time; a predetermined number of data output buffers for receiving and buffering the predetermined number of pair of data generated from each of the predetermined number of main buffers, in response to a data output buffer control signal; and data output buffer control signal generating means for generating the data output buffer control signal being enabled in response to a control signal and disabled after a lapse of a predetermined time from the point of time at which each of the pair of data output from the predetermined number of main buffers reaches the stable complementary levels.
To accomplish the other object of the present invention, there is provided a data read method in a semiconductor memory device comprising a plurality of memory cell array blocks, the method comprising the steps of: amplifying a predetermined number of pairs of data output from each of the plurality of memory cell array blocks in response to a first control signal, to generate a first pair of data; resetting the first pair of data and generating a second pair of data whose level is converted when the first pair of data reaches stable complementary levels in response to a second control signal, the second pair of data being reset after a lapse of a predetermined time; and buffering and outputting of the second pair of data in response to a fourth control signal, the fourth control signal being enabled in response to a third control signal, the fourth control signal converting its level when the second pair of data reaches the stable complementary levels, and then being disabled after a lapse of a predetermined time.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5517461 (1996-05-01), Umo et al.
patent: 5592435 (1997-01-01), Mills et al.
patent: 5812490 (1998-09-01), Tsukude

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