Semiconductor memory device and data read method of the same

Details Semiconductor memory device and data read method of the same Semiconductor memory device and data read method of the same

2006-09-12

2006-09-12

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000, C365S189070

Reexamination Certificate

active

07106653

ABSTRACT:
The present invention discloses a semiconductor memory device that includes first and second memory banks. A first control signal generating circuit generates a first control signal responsive to an external clock. A first data output circuit transmits a first output data responsive to the first control signal. An internal clock signal generating circuit outputs first and second buffered clock signals responsive to the external clock. A second control signal generating circuit generates a second control signal responsive to the first buffered clock signal and the first control signal. A second data output circuit transmits a second output data responsive to the second control signal. A third data output circuit transmits a third output data responsive to the first and second buffered clock signals. The present invention prevents data read errors resulting from variations in power supply voltage and temperature.

REFERENCES:
patent: 5990730 (1999-11-01), Shinozaki
patent: 2005/0195663 (2005-09-01), Kwak
patent: 2002-304885 (2002-10-01), None
patent: 1999-48159 (1999-07-01), None
patent: 1999-86847 (1999-12-01), None
English language abstract of Korean Publication No. 1999-86847.
English language abstract of Korean Publication No. 1999-48159.
English language abstract of Japanese Publication No. 2002-304885.

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