Semiconductor memory device and data read and write method...

Static information storage and retrieval – Addressing – Sync/clocking

Reexamination Certificate

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Details

C365S219000, C365S221000, C365S189050, C365S194000, C365S238500

Reexamination Certificate

active

07376041

ABSTRACT:
A semiconductor memory device includes a memory cell array to store data; a data input portion to output data to the memory cell array in response to a write control signal; a data output portion to output data from the memory cell array in response to a read control signal; a data I/O gate to transmit data outputted from the data input portion to the memory cell array in response to the write control signal, and transmitting data outputted from the memory cell array to the data output portion in response to the read control signal; and a data I/O controller to generate the read control signal and the write control signal having a smaller minimum cycle time than a minimum cycle time of the read control signal. The semiconductor memory device has an improved operation performance compared to one having a low operation frequency within an operable frequency range.

REFERENCES:
patent: 5596540 (1997-01-01), Diem et al.
patent: 6229758 (2001-05-01), Agata
patent: 6809984 (2004-10-01), Nagano
patent: 6865135 (2005-03-01), Choi
patent: 6901025 (2005-05-01), Ooishi
patent: 2001-176267 (2001-06-01), None
patent: 2001-0050549 (2001-06-01), None
English language abstract of Korean Publication No. 2001-0050549.
English language abstract of Japanese Publication No. 2001-176267.

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