Semiconductor memory device and control method thereof

Details Semiconductor memory device and control method thereof Semiconductor memory device and control method thereof

2005-12-20

2005-12-20

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S233100

Reexamination Certificate

active

06977859

ABSTRACT:
A semiconductor memory device, which can hides a delay in a refresh operation from an outside for speeding up operation, comprises a memory cell including first and second transistors connected between a bit line for a write system and a bit line for a read system, and a capacitor C for data storage, in which a word line for a write system and a word line for a read system are connected to control terminals of the two transistors, respectively, a circuit for comparing a refresh address with an address selected according to a read/write signal among read/write addresses from an address holding circuit for holding input address signal and performing control so that if a mismatch is detected, a read/write operation using one of the read and write systems, selected by the read or write address and a refresh operation using the other of the read and write systems, selected by the refresh address are performed in parallel and if a match has been detected, the read or write operation using the word line and the bit line associated with one of the read and write systems is performed.

REFERENCES:
patent: 6166980 (2000-12-01), Chun
patent: 6636449 (2003-10-01), Matsuzaki
patent: 6744684 (2004-06-01), Arimoto et al.

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