Semiconductor memory device and control method thereof

Details Semiconductor memory device and control method thereof Semiconductor memory device and control method thereof

2005-01-25

2005-01-25

Mai, Son (Department: 2818)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S222000

Reexamination Certificate

active

06847540

ABSTRACT:
A semiconductor memory device, in which a cell plate potential does not fluctuate even when the device state is changed from a state without stored charge in all charge storage nodes of the cell capacitors at power-on to an access operation state, comprises NMOS transistors M1to Mk for connecting a line VPR as a feeder for a reference voltage VPR from a reference voltage generation circuit with a line VCP as a feeder for a reference voltage VCP from the reference voltage generation circuit in each of cell blocks B1to Bk. Gate terminals of the NMOS transistors M1to Mk are connected to a common signal φCPR. The signal φCPR outputs a positive logical level at a predetermined time after power-on. By providing the NMOS transistors M1to Mk for short-circuiting the line VPR with the line VCP in each of the cell blocks B1to Bk, both lines are short-circuited in each of the cell blocks B1to Bk.

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