Semiconductor memory device and control method thereof

Details Semiconductor memory device and control method thereof Semiconductor memory device and control method thereof

2002-10-01

2004-04-06

Tran, Michael (Department: 2818)

Static information storage and retrieval

Read/write circuit

Signals

C365S195000

Reexamination Certificate

active

06717868

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a control method thereof capable of executing data-access to a corresponding memory cell in response to address transition under active state. More particularly, it relates to a semiconductor memory device and a control method thereof that need to remedy data-storage level of memory cells that has lowered during data-access of memory cells, after the data access is executed.
2. Description of Related Art
A semiconductor memory device such as DRAM stores data in memory cells in a form of charges stored in cell capacitors. For data-access with respect to such type of semiconductor memory, a cell capacitor is firstly connected to a bit line and amplified by a sense amplifier. After that, the bit line is connected to a data line, whereby input/output of data-can be executed. Voltage level of data lines may be limited lower compared with that of bit lines so as to secure high-speed access performance. Furthermore, in case a data line is shared by a plurality of bit lines, voltage level of the data line may possibly be precharged or equalized to predetermined voltage level before the data line is connected to one of the bit lines. Accordingly, even though the data line with any voltage level is connected to one of the bit lines, voltage level of the bit line and that of the data line differ from each other. Therefore, voltage level of the bit line is likely to receive voltage interference from the data line. For example, at bit line, high-level voltage lowers whereas low-level voltage rises. In this case, a bit line is connected to a cell capacitor. Accordingly, data-storage level lowers simultaneously and so-called disturb phenomenon occurs. Bit lines under the influence of voltage interference due to disturb phenomenon are electrically separated from data lines. After that, a sense amplifier amplifies voltage of bit lines to get their voltage level back to before-disturb-phenomenon.
Furthermore, as one of the data-access functions provided for the above semiconductor memory, address-access function is significant. The address-access function is to execute data-access to memory cells corresponding to inputted addresses transitions made on demand while the semiconductor memory is in active state. With this manner of the address-access function, data held in a plurality of bit lines are amplified. As address transition is made on demand, a bit line corresponding to the address transition is selected and connected to a data line. Address access thus can be realized. This function enables a semiconductor memory device to receive addresses transition on demand.
FIG. 7
shows operational waveforms for illustrating address access function of a semiconductor memory that accompanies disturb phenomenon at the time of data access. When the semiconductor memory is activated by an external instruction signal, a word line WL starts up. Subsequently, a plurality of bit lines BL
0
through BLx are connected to memory cells and differential amplification is applied to pairs of bit lines (BL
0
Z and BL
0
X through BLXZ, and BLXX). When an address ADD makes address transition to an address signal ADD
0
, a column selecting line CL
0
is driven in a manner of pulse drive so as to connect a bit line BL
0
, corresponding to the address signal ADD
0
, to a data line. Since data lines different in their voltage level are connected to a pair of bit lines (BL
0
Z and BL
0
X) to which differential amplification are applied, the pair of bit lines (BL
0
Z and BL
0
X) receive voltage interference and difference of voltage level lowers. After the column selecting line CL
0
is selected, this voltage level that has lowered gets back to before-disturb-phenomenon voltage level on condition that differential amplification continues. As an address ADD makes address transition to an address signal ADD, the column selecting line CL
0
is selected within an access time tAAC
0
(see (
1
) in FIG.
7
).
The address ADD makes address transition on demand asynchronously while the semiconductor memory is set in active state in accordance with an external instruction signal (the external instruction signal is a low-level signal in FIG.
7
). Accordingly, final address transition is made in simultaneous with deactivation timing of an external instruction signal. In
FIG. 7
, the address transition to the address signal ADDX corresponds to the final address transition. In this case, although it depends on internal circuit structure of the semiconductor memory and operation-speed of the internal circuit, there may occur a case that a word line WL is deactivated along with deactivation of the external instruction signal while a column-selecting line CLX is selected in response to address access corresponding to address transition to the address signal ADDX. That is, upon selection of the column-selecting line CLX, bit lines and data lines are connected to one another and a word line WL gets deactivated while disturb phenomenon occurs. As a result, memory cells can store electric charges that have low voltage level due to the disturb phenomenon, whereby data holding characteristic deteriorates (see (
2
) in FIG.
7
).
Conventionally, there has been conceived circuit structure as shown in
FIG. 8
so as prevent data holding characteristic from deteriorating.
FIG. 9
shows operational waveforms directed to the circuit structure of FIG.
8
. Address signals CAn and external instruction signals Exn both inputted from an external are inputted to a semiconductor memory as signals CAGn and signals EXGn, respectively, through address buffers
10
. . .
10
, input buffers
18
( . . .
18
), and glitch cancellers
12
. . .
12
and
20
( . . .
20
) for eliminating glitch noises. Delay circuits
14
. . .
14
are arranged between the glitch cancellers
12
. . .
12
and a column selecting circuit
16
. Delay time &tgr;D corresponds to time for a signal CAGn to propagate to the column selecting circuit
16
as delay signals CAGDn. This delay time &tgr;D is set longer than time required for discriminating signals EXGn by an external-instruction discriminating circuit
22
and outputting a precharge signal PRE. Thereby, delay signals CAGDn propagate delaying against a precharge signal PRE. As a result the precharge signal PRE deactivates the column selecting circuit
16
to mask column-selecting signal CLn. Therefore, a column-selecting signal CLn and a word line WL are never output concurrently.
It should be noted that there are a plurality kinds of external instruction signals EXn and combinations of those signals EXn set various instructions. Therefore, the external-instruction discriminating circuit
22
is arranged. In case single external instruction signal EXn sets an instruction, the external-instruction discriminating circuit
22
is not required.
The above related art directed to FIG.
8
and
FIG. 9
includes the delay circuits
14
. . .
14
so as to add delay time &tgr;D to input paths of address signals CAn with deactivation timing derived from external instruction signals EXn. Thereby, propagation time of delay signals CAGDn, derived from transition of the address signals CAn, is delayed so that selection of a column-selection signal CLn and deactivation of a word line WL should not be done concurrently. This system is to prevent data holding characteristic for memory cells from deteriorating.
However, since the delay circuits
14
are arranged on propagation paths for address signals, delay time &tgr;D is added every time address signals are propagated. Therefore, delay time &tgr;D is always forcedly added to access time tAAC
0
which is inherent shortest access time feasible with the circuit structure, i.e., address access time tAAC=tAAC
0
+&tgr;D. Due to insertion of the delay circuit, high-speed-access ability inherently given to such structured circuit cannot be shown. This is problematic because demand on high-speed-access operation cannot fully be satisfied.
Furthermore, it is possibl

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