Semiconductor memory device and control method thereof

Details Semiconductor memory device and control method thereof Semiconductor memory device and control method thereof

2007-06-25

2010-12-07

Le, Dieu-Minh (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S005110

Reexamination Certificate

active

07849357

ABSTRACT:
A semiconductor memory device has a semiconductor memory which includes the first central management block storing an address translation table, a free table for registering only an effective block address, the first bad block table, and a reserved table, and a controller configured to control a substitution block address acquired from the reserved table to substitute a bad block address when the bad block address is generated in the address translation table.

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U.S. Appl. No. 11/683,604, filed Mar. 8, 2007, Takeshi Nakano.

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