Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2007-06-25
2010-12-07
Le, Dieu-Minh (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S005110
Reexamination Certificate
active
07849357
ABSTRACT:
A semiconductor memory device has a semiconductor memory which includes the first central management block storing an address translation table, a free table for registering only an effective block address, the first bad block table, and a reserved table, and a controller configured to control a substitution block address acquired from the reserved table to substitute a bad block address when the bad block address is generated in the address translation table.
REFERENCES:
patent: 5335328 (1994-08-01), Dunn et al.
patent: 5459850 (1995-10-01), Clay et al.
patent: 5740349 (1998-04-01), Hasbun et al.
patent: 6845438 (2005-01-01), Tanaka et al.
patent: 7139864 (2006-11-01), Bennett et al.
patent: 7328301 (2008-02-01), Eilert et al.
U.S. Appl. No. 11/683,604, filed Mar. 8, 2007, Takeshi Nakano.
Kabushiki Kaisha Toshiba
Le Dieu-Minh
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
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