Semiconductor memory device and control method

Details Semiconductor memory device and control method Semiconductor memory device and control method

2003-02-21

2004-08-03

Auduong, Gene N. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Serial read/write

C365S189011, C365S233100

Reexamination Certificate

active

06771552

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a DDR (Double Data Rate) SDRAM (Synchronous DRAM).
2. Description of the Related Art
In DDR-SDRAM, a system clock CLK supplied from the outside and a data strobe (hereinbelow abbreviated as “DQS”) signal that is received as input and supplied as output in synchronization with transfer data are used to control data writing and data reading operations.
The DQS signal is a serial pulse signal of the same period as system clock CLK in which the skew with system clock CLK and the pulse width are prescribed by the standards of JEDEC (Joint Electron Device Engineering Council).
The first to third prior-art examples described below are known methods of using this system clock CLK and DQS signal to control data writing and data reading operations.
3. First Example of the Prior Art
We next refer to
FIG. 1
, which is a block diagram showing the construction of the semiconductor memory device of the first prior-art example.
As shown in
FIG. 1
, the semiconductor memory device of the first example of the prior art is a construction that includes: memory unit
101
in which data are stored, peripheral circuit unit
102
for controlling the operations of writing data to and reading data from memory unit
101
, and internal voltage generation circuit
103
for generating various power supply voltages that are supplied to memory unit
101
and peripheral circuit unit
102
.
Memory unit
101
is provided with: memory cell array
111
that is constructed from a plurality of memory cells that are arranged in a lattice form, sense amplifier
112
and read amplifier
113
for reading data that are stored in memory cells, write amplifier
114
for writing data to memory cells, and Y-decoder
115
and X-decoder
116
for decoding address signals that are used for accessing memory cells in which data are written or read. Sense amplifier
112
is provided with switches (not shown in the figures) for connecting write amplifier
114
and read amplifier
113
to each of the bit lines BL of memory cell array
111
.
Peripheral circuit unit
102
is a construction that includes: FIFO memory
121
for temporarily holding write data, which are data that are the object of writing that are applied as input to write amplifier
114
; FIFO memory
122
for temporarily holding read data, which are data that are the object of reading and that are supplied as output from read amplifier
113
; timing generation circuit
123
for generating, from system clock CLK that is supplied from the outside, various timing signals for causing the semiconductor memory device to operate at prescribed timings; command decoder
124
for decoding various control commands that are supplied from the outside for setting the semiconductor memory device to prescribed operation modes; read-system control circuit
125
for controlling the operations of reading data from memory cell array
111
in accordance with the output signals of timing generation circuit
123
and command decoder
124
; write-system control circuit
126
for controlling the operations of writing data to memory cell array
111
in accordance with the output signals of timing generation circuit
123
and command decoder
124
; latch circuit
128
for temporarily holding address signals that are supplied from the outside; refresh counter
129
for controlling the refresh operation; Y-system control circuit
130
for controlling the operations of accessing the Y-(column-) system of memory cell array
111
in accordance with the output signals of timing generation circuit
123
and command decoder
124
; X-system control circuit
131
for controlling the operations of accessing the X-(row-) system of memory cell array
111
in accordance with the output signals of timing generation circuit
123
and command decoder
124
; predecoder remedy circuit
132
that is used in the Y-system when a defect occurs in a memory cell for switching the defective memory cell to a spare memory cell; and predecoder remedy circuit
133
that is used in the X-system when a defect occurs in a memory cell for switching the defective memory cell to a spare memory cell.
Input circuits
134
1
-
134
3
are buffer circuits by way of which system clock CLK (/CLK), control commands (such as /RAS, /CAS, /WE, and /CS), and address signals Add, respectively, are supplied to peripheral circuit unit
102
. Data (write data) that are written to memory cell array
111
are supplied to FIFO memory
121
by way of input circuit
134
4
, and data that are read from memory cell array
111
are supplied to the outside by way of output circuit
135
1
, which is a buffer circuit. Similarly, the DQS signal that is supplied from the outside is supplied to peripheral circuit unit
102
by way of input circuit
134
5
, and the DQS signal that is generated at read-system control circuit
125
is fed to the outside by way of output circuit
135
2
.
DDR-SDRAM is a prefetch memory for collecting write data that are held in a plurality of FIFO memories and transferring the data to write amplifiers. When, for example, the burst length is 4 and the prefetch number is 4 in such a prefetch memory, four items of write data are successively received as input with every write command, and the four items of write data are collected and transmitted from a FIFO memory to a write amplifier. Alternatively, when the burst length is 8 and the prefetch number is 4, eight items of write data are successively received as input for every write command, collected for every four items of write data (in units of the prefetch number), and transmitted from a FIFO memory to a write amplifier.
Thus, although not shown in
FIG. 1
, FIFO memories
121
and
122
are provided in a number that equal to the bits of write data and read data (such as 8, 16, or 32 bits), and write amplifiers
114
and read amplifiers
113
are provided in a number equal to the prefetch number (such as 2 or 4) for each of the bits of write data and read data. Consequently, FIFO memories
121
and
122
and write amplifiers
114
and read amplifiers
113
are each connected by GIO lines that are equal in number to the product of the number of bits of write data and read data and the prefetch number. Further, write amplifiers
114
, read amplifiers
113
, and memory cell array
111
are connected by LIO lines that are equal in number to the product of the number of bits of write data and read data and the prefetch number.
We next refer to the timing chart of
FIG. 2
to explain the operations of writing and reading data of the semiconductor memory device of the first prior-art example shown in FIG.
1
.
FIG. 2
shows data writing and reading operations in which the write latency is 1, the read latency is 2, the burst length is 4, and the prefetch number is 4.
The semiconductor memory device of the first prior-art example is a construction in which the operations of writing data to and reading data from memory cell array
111
are all controlled by synchronizing with system clock CLK.
As shown in
FIG. 2
, when data are written to the semiconductor memory device of the first prior-art example, the plurality of items of write data (DQ) that are successively received in synchronization with each rising edge and falling edge of the DQS signal are both converted to parallel data and temporarily held by FIFO memory
121
. The data are then transferred (GIO) to write amplifier
114
in synchronization with the rising edge of the first system clock CLK (CLK=3) following completion of data input (of the prefetch number of items of data). GIO in
FIG. 2
shows the state when write data #0-#3 are transmitted in parallel.
When the semiconductor memory device is set to write mode (WRIT) by a control command from the outside, a write command instructing the writing of data that is generated at command decoder
124
is supplied to Y-system control circuit
130
. In addition, a timing signal that is generated by timing generation circui

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