Semiconductor memory device and control method

Details Semiconductor memory device and control method Semiconductor memory device and control method

2011-08-02

2011-08-02

Dinh, Son T (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S063000, C365S189070, C365S189140

Reexamination Certificate

active

07990789

ABSTRACT:
A semiconductor memory device, in which a plurality of data output lines are commonly used by a plurality of banks, includes a plurality of gate circuits each of which are provided at each intermediate position of the plurality of the data output lines, and is controlled to be turned on during a normal operation mode and to be turned off at least when reading data during a parallel test mode, and a comparator circuit that inputs in parallel and compares a signal of each separated part of the each data output line separated by the plurality of the gate circuit being turned off.

REFERENCES:
patent: 6400623 (2002-06-01), Ohno
patent: 6438760 (2002-08-01), Wakefield et al.
patent: 2006/0123291 (2006-06-01), Kim
patent: 2000-40397 (2000-02-01), None

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