Semiconductor memory device and circuit layout of dummy cell

Details Semiconductor memory device and circuit layout of dummy cell Semiconductor memory device and circuit layout of dummy cell

2006-11-14

2006-11-14

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S190000, C365S156000

Reexamination Certificate

active

07136318

ABSTRACT:
A dummy cell includes two series-connected OFF-state transistors, one end of the series circuit which is formed by these two transistors is connected with a constant voltage source, and the other end of the series circuit is connected with a replica bit line. This suppresses a leak current flowing from the replica bit line to the dummy cell and therefore gives optimal start-up timing to a sense amplifier circuit.

REFERENCES:
patent: 5838612 (1998-11-01), Calligaro et al.
patent: 6549484 (2003-04-01), Morita et al.
patent: 6646938 (2003-11-01), Kodama
patent: 6760269 (2004-07-01), Nakase et al.
patent: 6982914 (2006-01-01), Ohtsuki et al.
patent: 6999367 (2006-02-01), Yamagami
patent: 9259589 (1997-10-01), None
patent: 2003036678 (2003-02-01), None

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