Semiconductor memory device and a method of redressing a...

Details Semiconductor memory device and a method of redressing a... Semiconductor memory device and a method of redressing a...

2007-09-25

2007-09-25

Mai, Son L. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S145000, C365S149000

Reexamination Certificate

active

11163732

ABSTRACT:
A semiconductor memory device has a non-auxiliary memory cell, an auxiliary memory cell, a first driver, and a second driver. The non-auxiliary memory cell is connected to a predetermined bit line and a first word line. The auxiliary memory cell is connected to the predetermined bit line and a second word line. The first driver operates the first word line. The second driver operates the second word line when the first driver operates the first word line.

REFERENCES:
patent: 5373471 (1994-12-01), Saeki et al.
patent: 5555212 (1996-09-01), Toshiaki et al.
patent: 5592428 (1997-01-01), Harrand et al.
patent: 6172921 (2001-01-01), Park et al.
patent: 6317355 (2001-11-01), Kang
patent: 6958945 (2005-10-01), Shore
patent: 7016215 (2006-03-01), Kamoshida et al.
patent: 2004/0114414 (2004-06-01), Kamoshida et al.

Affiliated with

Also associated with

Rating

Semiconductor memory device and a method of redressing a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device and a method of redressing a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device and a method of redressing a... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3745276