Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Patent
1997-06-19
1999-02-23
Zarabian, A.
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
3652335, G11C 1604
Patent
active
058751335
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention pertains to a semiconductor memory device such as a static random access memory ("RAM"); and, in particular, to a semiconductor memory device which widens the amplitude of data stored in memory cells by stepping up its word lines and an improved method for stepping up the word lines.
BACKGROUND OF THE INVENTION
In a semiconductor memory device, the data stored in memory cells may be incidentally destroyed by alpha rays, noise, or the like. This type of data destruction occurs more often when the amplitude of the data stored in the memory cells (i.e., the difference between the voltage of H level and L level) is decreased. Therefore, the influence of such data destruction is more important now that low voltage semiconductor memory devices are in greater demand.
Accordingly, Japanese Patent Laid-open Application Showa 58-169958 discloses a device in which the amplitude of the data in memory cells is widened as much as possible within the limit of a given power voltage. This conventional device will now be described with reference to FIGS. 1 and 2. FIG. 1 shows a step-up circuit for a conventional static RAM. As shown, a memory cell 10 is composed of four N-channel MOSFETs ("NMOS transistors") T20-T23 and two high resistance loads R1 and R2. Multiple memory cells 10 are arranged in matrix form and each memory cell 10 is connected to a word line WL and a pair of bit lines BL and /BL (a bar of BL). Each word line WL is long enough to be connected to 256 memory cells, and there are 512 word lines, for example. The pair of bit lines BL and /BL are used to write data in or read data out of the memory cells 10, and there are 1024 pairs of bit lines BL and /BL, for example.
Data buses DB and /DB are coupled to the pair of bit lines by means of a column gate 12, which is composed of four transistors T14-T17 controlled by row selective signals Y and /Y. Bit line load transistors T18 and T19 are connected between a power source (not shown) and the bit lines BL and /BL, respectively. A write-in circuit 14 is composed of two P-channel MOSFETs ("PMOS transistors") and two NMOS transistors T10-T13. An inverter composed of PMOS transistor T8 and NMOS transistor T9 functions as a word line driver 16, and there are as many word line drivers as the number of word lines WL. The word line driver 16 is driven by the output of a row selective decoder 18.
Further, a step-up control circuit 20 is composed of three PMOS transistors T1, T3, and T4, three NMOS transistors T2, T5, and T6, and a delay circuit 22. Additionally, a step-up circuit 24 is composed of a step-up capacitor C1 and a PMOS transistor T7.
Next, the operation of the conventional device will be described with reference to the timing chart of FIG. 2. In the device of FIG. 1, when data is written in the memory cell 10, the write-in signals IN and /IN are illustratively input to the write-in circuit 14, which is composed of four transistors T10-T14, so that the write-in signals IN and /IN go to logic L and H, respectively, at a time when the write enable signal /WE is set to a low level. In this case, the data bus /DB is raised up to the voltage of power source line Vdd when the write enable signal goes to logic L, as shown in FIG. 2. Further, the bit line /BL is also raised up to nearly Vdd, because the PMOS transistors and NMOS transistors that form the column gate 12 are connected in parallel and the bit line load transistor is a PMOS transistor.
Additionally, the write enable signal /WE is input to the step-up control circuit 20 and inverted to the write enable signal WE by means of transistors T1 and T2, which form an inverter. The write enable signal WE is supplied to the gates of the transistors T4 and T5. The write enable signal /WE is also delayed by the delay circuit 22 for a predetermined period to form the signal /WEd, which is supplied to the gates of transistors T3 and T6. The transistors T3-T6 form a NOR gate, so that node D goes to logic H only when both signals /WE and /WEd are at logic L. The transistor T
REFERENCES:
patent: 4730132 (1988-03-01), Watanabe et al.
Kumagai Takashi
Miyashita Koji
Tokuda Yasunobu
Seiko Epson Corporation
Zarabian A.
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