Semiconductor memory device and a method for arranging...

Details Semiconductor memory device and a method for arranging... Semiconductor memory device and a method for arranging...

2007-10-09

2007-10-09

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Interconnection arrangements

Reexamination Certificate

active

11262530

ABSTRACT:
The present invention discloses a semiconductor memory device and a method for arranging signal lines thereof. The semiconductor memory device including a first memory cell array, an IO control circuit and a second memory cell array arranged between the first memory cell array and the IO control circuit, includes: first IO signal lines for transmitting data between the first memory cell array and the IO control circuit, wherein the first IO signal lines are connected to first data loading locations of the first memory cell array and extend in a straight line to the IO control circuit; and second IO signal lines for transmitting data between the second memory cell array and the IO control circuit, wherein the second IO signal lines are connected to first data loading locations of the second memory cell array and extend to the IO control circuit, wherein lengths of the first IO signal lines starting from the first data loading locations of the first memory cell array to the IO control circuit are identical to lengths of the second IO signal lines starting from the first data loading locations of the second memory cell array to the IO control circuit.

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patent: 6125419 (2000-09-01), Umemura et al.
patent: 6728125 (2004-04-01), Hong
patent: 6831862 (2004-12-01), Tedrow et al.
patent: 07-154041 (1995-06-01), None

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