Semiconductor memory device allowing writing of desired data to

Static information storage and retrieval – Read/write circuit – Bad bit

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365203, 3652257, G11C 700

Patent

active

058963286

ABSTRACT:
In a defective cell write mode, a precharge potential generating circuit generates a precharge potential at a high level or a low level in accordance with an external control signal, and applies the potential to a bit line pair. Parallel to a fuse element provided between a main bit line precharge potential supply line and a sub bit line precharge potential supply line and is cut when a column is replaced by a redundancy column of memory cells, a pass transistor which is rendered conductive in the defective cell write mode is provided.

REFERENCES:
patent: 5666315 (1997-09-01), Tsukude et al.
patent: 5768206 (1998-06-01), McClure

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