Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-12-04
2002-01-01
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S189030, C365S230060
Reexamination Certificate
active
06335887
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device allowing an increased number of such devices to be tested simultaneously.
2. Description of the Background Art
A memory tester TST for testing semiconductor memory devices as shown in
FIG. 23
includes a motherboard MBD. Motherboard MBD has a plurality of mounting portions
51
for respectively mounting a plurality of chips thereon, and a connecting portion
52
corresponding to the memory tester side. The number of chips to be mounted onto motherboard MBD is determined according to the number of I/Os that is limited by memory tester TST.
Conventionally, for a chip of dynamic random access memory (DRAM) of x32-bit configuration, the number of testable I/Os is 32. Memory tester TST limiting the number of I/Os to 64 can test two such chips at the same time.
However, if the number of input/output terminals being used increases due to an increase of memory integration or a change of interfaces, the number of chips for simultaneous testing has to be reduced. This decreases productivity of the semiconductor memory devices like DRAMs.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a semiconductor memory device allowing an increased number of chips to be tested simultaneously.
The semiconductor memory device according to the present invention is a semiconductor memory device that allows selection of desired one of a plurality of word configurations. The semiconductor memory device includes: a test mode recognition circuit that inactivates a test mode signal in a normal operation mode and activates the test mode signal in response to an externally supplied test mode designating signal; a word configuration select circuit that selects, from a plurality of word configurations, a word configuration for use in the normal operation mode when receiving the inactive test mode signal from the test mode recognition circuit, and selects, from the plurality of word configurations, a word configuration that is smaller than that for use in the normal operation mode when receiving the active test mode signal from the test mode recognition circuit; and a terminal that inputs/outputs data to/from a memory cell array based on the word configuration selected by the word configuration select circuit.
According to the semiconductor memory device of the present invention, when the test mode signal is activated, the test is conducted selecting the word configuration that is smaller than that for use in the normal mode. Thus, a larger number of semiconductor memory devices can be mounted on a testing device and tested at the same time. As a result, it becomes possible to improve the throughput of testing of semiconductor memory devices.
Preferably, the semiconductor memory device further includes a word configuration determination signal generating circuit that generates a first word configuration determination signal when the inactive test mode signal is input from the test mode recognition circuit, and generates a second word configuration determination signal when the active test mode signal is input from the test mode recognition circuit. The word configuration select circuit selects the word configuration for use in the normal operation mode according to the first word configuration determination signal, and selects the word configuration that is smaller than that for use in the normal mode according to the second word configuration determination signal.
According to the semiconductor memory device of the present invention, when the test mode signal is activated, the test is conducted utilizing the word configuration that is smaller than that for use in the normal operation mode. Thus, it becomes possible to simultaneously mount a larger number of semiconductor memory devices on a testing device for testing. This improves the throughput of testing of semiconductor memory devices.
Still preferably, when the test mode signal is active, the word configuration determination signal generating circuit selects as a word configuration of the semiconductor memory device, the smallest word configuration from those selectable.
The test is thus conducted selecting the smallest possible word configuration. Accordingly, a maximum number of semiconductor memory devices can be mounted on the testing device, thereby maximizing the throughput of testing of the semiconductor memory devices.
The semiconductor memory device according to the present invention includes: m×n output terminals consisting of n short-circuited terminal groups each having m terminals being short-circuited in a test mode; a test mode recognition circuit that inactivates a test mode signal in a normal operation mode and activates the test mode signal in response to an externally supplied test mode designating signal; an output terminal select signal generating circuit that generates, when the test mode signal is active, a first output terminal select signal for causing data to be output from n output terminals each selected from respective one of the n short-circuited terminal groups, and generates, when the test mode is inactive, a second output terminal select signal for causing data to be output from the m×n output terminals; and an output terminal select circuit that selects either the n output terminals or the m×n output terminals according to the first or the second output terminal select signal generated.
For testing the semiconductor memory device having m×n output terminals, n output terminal groups are arranged, in each of which m output terminals are being short-circuited. Each one output terminal is selected from respective one of the n output terminal groups, and the n output terminals thus selected are used for the test. Accordingly, the semiconductor memory device can be tested with the number of output terminals reduced from m×n to n. As a result, it becomes possible to increase the number of semiconductor memory devices that can be mounted on the testing device simultaneously.
Preferably, the test mode recognition circuit inactivates all of m test mode signals in the normal operation mode, and activates any one of the m test mode signals in response to an externally supplied test mode designating signal. The output terminal select signal generating circuit generates, according to the m test mode signals, first and second output terminal select signals each made of m output terminal select signals. More specifically, when any one of the m test mode signals is activated, it generates the first output terminal select signal in which only one of the m output terminal select signals corresponding to the activated test mode signal is activated. When all the m test mode signals are inactivated, it generates the second output terminal select signal with all the m output terminal select signals being activated. The output terminal select circuit, when receiving the first output terminal select signal, selects n output terminals corresponding to the activated one of the m output terminal select signals.
Thus, the m output terminal select signals are generated corresponding to the m test mode signals. In the test mode, any one of the m test mode signals is activated, and the remaining test mode signals are inactivated. In response, only one output terminal select signal corresponding to the activated test mode signal is activated, and in turn, n output terminals are selected corresponding to the activated output terminal select signal. An output terminal select signal to be activated is changed by altering the one test mode signal to be activated among the m test mode signals. Different n output terminals are thus selected corresponding to the change of the output terminal select signal being activated. Meanwhile, in the normal operation mode, all the test mode signals are inactivated, the m output terminal select signals are all activated, so that the m×n output terminals are all selected.
As desc
Aoki Shigekazu
Asakura Mikio
Hamamoto Takeshi
Hirose Masakazu
Sawada Seiji
Le Thong
Mitsubishi Denki & Kabushiki Kaisha
Phan Trong
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