Semiconductor memory device allowing spare memory cell to be...

Details Semiconductor memory device allowing spare memory cell to be... Semiconductor memory device allowing spare memory cell to be...

2001-01-05

2003-04-08

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S200000, C365S222000

Reexamination Certificate

active

06545921

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor memory devices and particularly to those having a redundant, repairing spare memory cell.
2. Description of the Background Art
Recently there has been provided a semiconductor memory device having a memory cell array configuration to provide a wide data I/O width to accommodate some applications, such as an image processing requiring a wide memory band width.
Representatively, there has been developed a merged DRAM/logic with a logic portion and a dynamic random access memory (DRAM) both mounted on a single chip. In this memory, an I/O pin and an external bus that conventionally exist between a processor portion and a DRAM core can be eliminated to allow data to be transferred with high degree of freedom and a large number of global data input/output lines allowing data to be simultaneously input/output to/from the DRAM core can be provided to achieve a wide data I/O width.
In a merged memory/logic a logic portion and a DRAM core have much more global data input/output lines arranged therebetween than in a general-purpose memory, reaching more than 200 or more than 500 in number. In a merged memory/logic, a memory core incorporated therein is tested using data transmitted on such global data input/output lines, although a memory tester or a similar external test apparatus can only make a decision on limited data at a time. Furthermore, to efficiently test an operation a plurality of memory cores need to be tested simultaneously in parallel.
As such, the merged memory/logic typically has mounted therein a circuit operating in the operation test to select some of a large number of global data input/output lines arranged in parallel and output to an external test apparatus the data transmitted on the selected global data input/output line.
Furthermore, a large-scale memory core mounted in a merged memory/logic has a spare memory cell provided for each predetermined segment of regular memory cell arrays to repair a defective regular memory cell to improve the yield of the device. In general, a spare memory cell operation test is conducted separately from a regular memory cell operation test. Both of a result of testing a spare memory cell and that of testing a regular memory cell are used for determining a substitution pattern for redundancy to repair a defective memory cell.
A large-scale memory core has a large area occupied by spare memory cells. As such, it is important that not only a regular memory cell operation test but a spare memory cell operation test be conducted efficiently.
FIG. 12
is a block diagram for illustrating conventionally selecting output data in a testing operation.
FIG. 12
exemplarily illustrates that in the testing operation, hereinafter also referred to as the “test mode”, eight testing output data TDout are output for a single read operation.
With reference to
FIG. 12
, a memory cell array subject to an operation test is configured of a plurality of memory mats each corresponding to a predetermined segment of a regular memory cell array.
FIG. 12
exemplarily shows a memory cell array formed of eight memory mats MT
0
to MT
7
.
256 regular global data input/output lines GIO(
0
) to GIO(
255
) are arranged to transmit data input/output to/from a regular memory cell of the memory cell array. Each memory mat is provided with a spare memory cell arranged therefor, and to transmit data input/output to/from a spare memory cell there are provided spare global data input/output lines SGIO(
0
) to SGIO(
7
) for memory mats MT
0
to MT
7
, respectively.
Regular global data input/output lines GIO(
0
) to GIO(
255
) are divided into a plurality of groups of eight lines, which number corresponds to the number of the data output in the testing operation, and the eight regular global data input/output lines of each group are gathered at a respective one of internal node groups N
0
-N
31
. For example, at internal node group N
0
are gathered regular global data input/output lines GIO(
0
) to GIO(
7
).
To accommodate a spare memory cell operation test, spare select circuits
510
-
0
to
510
-
7
are provided for memory mats MT
0
to MT
7
, respectively. Each spare select circuit receives as an input thereof one of the regular global data input/output lines for a single memory mat and a spare global data input/output line and in response to a test mode signal STMOD outputs data transmitted on either one of the regular and spare global data input/output lines. Test mode signal STMOD is activated when a spare memory cell has its operation to be tested in the test mode, and it is otherwise inactivated.
For example, spare select circuit
510
-
0
receives regular global data input/output line GIO(
0
) and spare global data input/output line SGIO(
0
) and outputs data transmitted on spare global data input/output line SGIO(
0
) for active mode signal STMOD and data transmitted on regular global data input/output line GIO(
0
) for inactive mode signal STMOD.
Spare select circuits
510
-
0
to
510
-
7
operate in response to the common mode control signal STMOD. As such, if a spare memory cell has its operation to be tested, in each memory mat for any one of the plurality of node groups there can be read the data transmitted on a spare global data input/output line.
A selector circuit
520
selects any one of internal node groups N
0
to N
31
in response to select signals SEL
0
to SEL
4
and outputs eight data corresponding to the selected internal node group.
If a spare memory cell has its operation to be tested, select signals SEL
0
to SEL
4
can be changed to select internal node groups N
0
, N
4
, . . . , N
28
, corresponding to spare select circuits
510
-
0
to
510
-
7
, successively one at a time, to output data output from each memory mat and transmitted on a spare global data input/output line to an external testing apparatus.
If in such a configuration as above a spare memory cell has its operation tested, however, of eight testing output data from selector circuit
520
only one data corresponds to a spare memory cell and the other seven data are irrelevant to the spare memory cell operation test. This means that testing data are uselessly output. In the
FIG. 12
configuration, outputting the data transmitted on all of spare global data input/output lines SGIO(
0
) to SGIO(
7
) requires performing a read operation eight times. As such, the spare memory cell operation test is time-consuming. Furthermore, of a plurality of data output from selector circuit
520
the data output corresponding to a spare memory cell needs to be recognized by an external testing apparatus. This complicates a program in conducting the operation test.
In testing a spare memory cell, generating the test mode has a disadvantage, as will be described below.
FIG. 13
is a block diagram for illustrating conventionally decoding a command.
With reference to
FIG. 13
, any one of 2
3
=eight commands is produced according to a combination in level of three command control signals of a row address strobe signal /RAS, a column address strobe signal /CAS and a write enable signal /WE.
The produced command is any one of no-operation command (NOP), an activation command (ACT), a read command (READ), a write command (WRT), a precharge command (PRE), a mode set command (MST), an auto-refresh command (AREF) and a self-refresh command (SREF).
The group of these commands are produced by a logic gate group LG
50
. If mode set command MST is produced, a mode set sequence is also started. In the mode set sequence, one of a plurality of modes set in a mode table
530
is selected according to a combination in level of address signals A
0
to A
10
input to an address terminal.
When read command READ is produced, mode table
530
is referred to to selectively perform either one of an operation reading a regular memory cell and that reading a spare memory cell. Similarly, when write command WRT is produced, the mode table is referred to to perform an operation writing data to either on

Affiliated with

Also associated with

Rating

Semiconductor memory device allowing spare memory cell to be... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device allowing spare memory cell to be..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device allowing spare memory cell to be... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3034103