Semiconductor memory device allowing reduction of I/O terminals

Details Semiconductor memory device allowing reduction of I/O terminals Semiconductor memory device allowing reduction of I/O terminals

2003-02-12

2004-09-07

Elamin, A. (Department: 2116)

Electrical computers and digital data processing systems: input/

Input/output data processing

Peripheral configuration

C711S100000, C711S101000, C711S154000, C711S170000, C711S173000

Reexamination Certificate

active

06789137

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device allowing reduction of I/O terminals in a slow operation mode.
2. Description of the Background Art
A DDR-SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) is now available as a semiconductor memory device, which has a large capacity and can perform fast input/output of data.
Referring to
FIG. 33
, a DDR-SDRAM
200
includes an address buffer
210
, a clock buffer
220
, a control signal buffer
230
, a control circuit
240
, a mode register
250
, a memory cell array
260
, a DLL (Delay Locked Loop)
270
, an I/O buffer
280
, a QS buffer
290
and data buses BS
1
and BS
2
.
Address buffer
210
externally receives addresses A
0
-A
12
and bank addresses BA
0
and BA
1
, and buffers received addresses A
0
-A
12
and bank addresses BA
0
and BA
1
. Address buffer
210
provides buffered addresses A
0
-A
12
and bank addresses BA
0
and BA
1
to control circuit
240
in synchronization with clocks BUFF_CLK and BUFF_/CLK sent from clock buffer
220
.
Clock buffer
220
externally receives clocks CLK and /CLK as well as a clock enable signal CKE, and buffers received clocks CLK and /CLK as well as received clock enable signal CKE with an internal reference voltage INTVREF. Reference voltage INTVREF has the same voltage as an externally received reference voltage VREF. Clock buffer
220
provides buffered clocks BUFF_CLK and BUFF_/CLK to control signal buffer
230
, control circuit
240
and DLL
270
, and provides buffered clock enable signal CKE to control circuit
240
.
Control signal buffer
230
externally receives a chip select signal /CS, a row address strobe signal /RAS, a column address strobe signal /CAS, a write enable signal /WE and a data mask signal DM, and buffers the received control signals such as chip select signal /CS with reference voltage INTVREF. Control signal buffer
230
provides the buffered control signals such as chip select signal /CS to control circuit
240
in synchronization with clocks BUFF_CLK and BUFF_/CLK sent from clock buffer
220
.
Control circuit
240
determines the next rising of clocks BUFF_CLK and BUFF_/CLK as valid if clock enable signal CKE was at an H (logical high) level at the time of rising of clocks BUFF_CLK and BUFF_/CLK received from clock buffer
220
. If clock enable signal CKE was at an L (logical low) level at the time of rising of clocks BUFF_CLK and BUFF_/CLK, control circuit
240
determines the next rising of clocks BUFF_CLK and BUFF_/CLK as invalid.
When clocks BUFF_CLK and BUFF_/CLK are determined as valid, control circuit
240
controls semiconductor memory device
200
based on chip select signal /CS, row address strobe signal /RAS, column address strobe signal /CAS, write enable signal /WE and data mask signal DM received from control signal buffer
230
.
More specifically, control circuit
240
recognizes the selection of semiconductor memory device
200
based on chip select signal ICS at L-level, and recognizes the nonselection of semiconductor memory device
200
based on chip select signal /CS at H-level. Control circuit
240
selects one of all of a plurality of banks included in memory cell array
260
based on bank addresses BA
0
and BA
1
sent from address buffer
210
. Further, control circuit
240
determines addresses A
0
-A
12
, which are received from address buffer
210
in accordance with the timing of switching of row address strobe signal /RAS from H-level to L-level, as a row address, and provides the row address to memory cell array
260
in synchronization with clocks BUFF_CLK and BUFF_/CLK sent from clock buffer
220
.
Further, control circuit
240
determines addresses A
0
-A
12
, which are received from address buffer
210
in accordance with the timing of switching of column address strobe signal /CAS from H-level to L-level, as a column address, and provides the column address to memory cell array
260
in synchronization with clocks BUFF_CLK and BUFF_/CLK sent from clock buffer
220
.
Control circuit
240
recognizes the data write mode or data read mode based on write enable signal /WE. In the write mode, control circuit
240
controls I/O buffer
280
such that write data sent from I/O terminals DQ
0
-DQ
7
may be provided to memory cell array
260
in synchronization with an internal data strobe signal INTDQS sent from QS buffer
290
, and also controls QS buffer
290
such that internal data strobe signal INTDQS prepared by buffering an externally supplied data strobe signal DQS is provided to I/O buffer
280
. In the read mode, control circuit
240
controls I/O buffer
280
such that the data read from memory cell array
260
via data bus BS
2
is provided to I/O terminals DQ
0
-DQ
7
in synchronization with period signal DLLCLK_P or DLLCLK_N sent from DLL
270
, and also controls QS buffer
290
such that period signal DLLCLK_P or DLLCLK_N sent from DLL
270
is provided to an I/O terminal DQS.
Control circuit
240
controls I/O buffer
280
based on data mask signal DM. More specifically, control circuit
240
operates in the write mode to control I/O buffer
280
based on data mask signal DM at H-level such that the write data may not be written into memory cell array
260
while data mask signal DM is at H-level, and to control I/O buffer
280
based on data mask signal DM at L-level such that all the write data may be written into memory cell array
260
. Further, control circuit
240
operates in the read mode to deactivate I/O buffer
280
based on data mask signal DM at H-level and to activate I/O buffer
280
based on data mask signal DM at L-level.
Further, control circuit
240
controls the timing for actually reading the data after instruction of the data read operation based on a CAS latency set by mode register
250
, and activates or deactivates DLL
270
in accordance with the instruction sent from mode register
250
.
Mode register
250
sets a CAS latency CL and provides it to control circuit
240
. Mode register
250
instructs control circuit
240
to activate or deactivate DLL
270
.
Memory cell array
260
includes the plurality of banks, and stores the data.
DLL
270
produces period signals DLLCLK_P and DLLCLK_N based on clocks BUFF_CLK and BUFF_/CLK sent from clock buffer
220
, and provides these period signals DLLCLK_P and DLLCLK_N to I/O buffer
280
and QS buffer
290
.
In the write mode, I/O buffer
280
writes the write data sent from I/O terminals DQ
0
-DQ
7
into memory cell array
260
in synchronization with internal data strobe signal INTDQS sent from QS buffer
290
. In the read mode, I/O buffer
280
provides the read data read from memory cell array
260
via data bus BS
2
to I/O terminals DQ
0
-DQ
7
in synchronization with period signals DLLCLK_P and DLLCLK_N sent from DLL
270
.
In the write mode, QS buffer
290
buffers externally supplied data strobe signal DQS, and provides buffered internal data strobe signal INTDQS to I/O buffer
280
. In the read mode, QS buffer
290
provides period signals DLLCLK_P and DLLCLK_N received from DLL
270
to I/O terminal DQS.
Data bus BS
1
provides the control signals such as addresses A
0
-A
12
and row address strobe signal /RAS, which are sent from control circuit
240
, to memory cell array
260
. Data bus BS
2
transmits the write data and read data between memory cell array
260
and I/O buffer
280
.
Referring to
FIG. 34
, description will now be given on the operation of writing data into memory cell array
260
in DDR-SDRAM
200
. It is assumed that DDR-SDRAM
200
is externally supplied with reference voltage VREF, and clock buffer
220
, control signal buffer
230
and QS buffer
290
receive internal reference voltage INTVREF having the same voltage level as reference voltage VREF.
When the write operation starts, clocks CLK and /CLK as well as clock enable signal CKE are externally supplied to DDR-SDRAM
200
. Clock buffer
220
buffers clocks CLK and /CLK, and provides buffered clocks BUFF_CLK and BUFF_/

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