Semiconductor memory device allowing high-speed operation of...

Details Semiconductor memory device allowing high-speed operation of... Semiconductor memory device allowing high-speed operation of...

1999-06-03

2001-01-09

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S230030, C365S202000, C365S190000, C365S189050

Reexamination Certificate

active

06172918

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to an arrangement for reducing an access time. More specifically, the present invention relates to an arrangement for driving an internal data line pair at a high speed.
2. Description of the Background Art
In a semiconductor memory device, an increase in storage capacity leads to an increase in the number of memory cells. Accordingly, bit lines and internal data lines become longer. As the bit lines and the internal data lines for transmitting data get longer, associated parasitic capacitance increases. In order to reduce such parasitic capacitance to transfer data at a high speed, a hierarchical I/O line arrangement is utilized in which signal lines for transmitting data are divided.
FIG. 23
is a schematic representation of an arrangement of an array portion of a conventional semiconductor memory device. In
FIG. 23
, a memory array MA is divided into a plurality of memory blocks MB00-MBmn. Memory blocks MBi0-MBin (i=0-m) arranged in alignment in a row-direction form a row block and share a word line. Memory blocks MB0j-MBmj (j=0-n) arranged in alignment in a column-direction share a column select line extending from a column decoder. Each of memory blocks MB00-MBmn has memory cells arranged in a matrix of rows and columns.
For each of memory blocks MB00-MBmn, a local data line pair LIO is disposed. In one example, in a column block including memory blocks MB00-MBm0, local data line pairs LIOa and LIOb are arranged on either side in the column-direction of a memory block MBiO. The local data line pair disposed between adjacent memory blocks MBiO and MB (i+1)0 in the column-direction is shared by these adjacent memory blocks.
In the column block including memory blocks MB0n-MBmn, local data line pairs LIOc and LIOd are disposed corresponding to each memory block. Similarly in this column block, local data line pairs LIOc and LIOd are shared by adjacent memory blocks in the column-direction.
A global data line pair GIO extending in the column-direction is provided in common to the memory blocks in a column block. Global data line pair GIO is coupled through a block select gate BSG to a local data line pair contained in a corresponding column block. In
FIG. 23
, local data line pair LIOa is coupled to a global data line pair GIOa via a block select gate BSGa, and local data line pair LIOb is coupled to a global data line pair GIOb via a block select gate BSGb. In addition, local data line pair LIOc is coupled to a global data line pair GIOc via a block select gate BSGc, and local data line pair LIOd is coupled to a global data line pair GIOd via a block select gate BSGd. These block select gates BSGa-BSGd are rendered conductive according to a row block select signal. Thus, in one column block, one memory block is selected, and the corresponding local data line pair is coupled to the corresponding global data line pair GIO through a block select gate.
Global data line pairs GIOa-GIOd are coupled in common to a write/read circuit WRC. Write/read circuit WRC includes a write driver for transmitting write data and a main amplifier for amplifying memory cell data. Write/read circuit WRC is coupled via a main data line pair MIO to an input/output buffer circuit, not shown. In the write/read circuit WRC, a write circuit or a read circuit corresponding to a selected column block is activated according to a column block select signal.
FIG. 24
is a diagram representing the arrangement of a portion related to a memory block in a memory array shown in FIG.
23
. In a memory block MB, memory cells MC are disposed in a matrix of rows and columns. For each column of memory cells, a bit line pair BLP is disposed, and for each row of memory cells, a word line WL is disposed. The word line WL is provided in common to the memory blocks included in a row block.
FIG. 24
shows representatively a word line WL, a bit line pair BLP, and a memory cell MC disposed corresponding to an intersection of bit line pair BLP and word line WL. Bit line pair BLP includes bit lines BL and ZBL for transmitting complementary data signals. Memory cell MC is disposed corresponding to an intersection of bit line BL or ZBL and word line WL. In
FIG. 24
, memory cell MC is disposed at an intersecting portion of bit line BL and word line WL.
Bit line pair BLP is coupled to a sense amplifier SA via a bit line isolating gate BIG. Sense amplifier SA is shared by memory block MB and another memory block not shown. Bit line isolating gate BIG is made to conduct in response to a bit line isolating instruction signal &phgr;BLI. When the other memory block sharing the same sense amplifier SA is selected, bit line isolating instruction signal &phgr;BLI attains a low or logic “L” level, causing memory block MB to be isolated from sense amplifier SA.
Sense amplifier SA is coupled to a local data line pair LIO through a column select gate CSG rendered conductive in response to a column select signal Y on a column select line CSL. Local data line pair LIO includes local data lines LI/O and ZLI/O provided corresponding to bit lines BL and ZBL, for transmitting complementary data signals.
Local data line pair LIO is connected to global data line pair GIO via a block select gate BSG rendered conductive in response to a row block select signal &phgr;RB. Global data line pair GIO also includes complementary data lines GI/O and ZGI/O and is coupled to a main amplifier MAP.
Each of bit line isolating gate BIG, column select gate CSG, and block select gate BSG is formed by a transfer gate consisting of an MOS transistor. Now, the operation will be briefly described.
First of all, when word line WL is selected according to an address signal, the voltage of word line WL is raised and the information stored in memory cell MC is transmitted to bit line BL. Bit line isolating instruction signal &phgr;BLI is at a high or logic “H” level, and bit lines BL and ZBL are coupled to sense amplifier SA. A paired memory block, not shown, is isolated from sense amplifier SA. When data is read from memory cell MC, sense amplifier SA, in turn, is activated and differentially amplifies the voltages of bit lines BL and ZBL. Since the data from the memory cell is not read out on bit line ZBL, the voltage on bit line BL is amplified, with the voltage on bit line ZBL used as the reference voltage. After differentially amplifying the voltage of bit lines BL and ZBL, sense amplifier SA holds the amplified voltages.
Thereafter, the column select operation begins. Column select signal Y transmitted from the column decoder (not shown) on column select line CSL attains the logic “H” level of the selected state, and column select gate CSG is made to conduct, thus allowing the data held by sense amplifier SA to be transmitted on local data line pair LIO. Block select gate BSG is rendered conductive according to row block select signal ORB while the word line is selected, and connects local data line pair LIO to global data line pair GIO. Therefore, when column select gate CSG is made to conduct and data is transmitted on local data line pair LIO, the data on local data line pair LIO is transmitted to global data line pair GIO via block select gate BSG. The data on global data line pair GIO is amplified by main amplifier MAP and is transmitted to an output buffer circuit, not shown.
Local data line pair LIO is provided only for memory block MB. The number of column select gates CSG connected to local data line pair LIO is relatively small so that the parasitic capacitance of local data line pair LIO is also relatively small. Moreover, global data line pair GIO is provided in common to the memory blocks in the column block and only block select gates BSG are connected to global data line pair GIO so that the parasitic capacitance of global data line pair GIO is also relatively small. Thus, since the parasitic capacitance of local data line pair LIO and global data line pair GIO is relatively small, data may be transm

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