Semiconductor memory device allowing high-speed activation of in

Details Semiconductor memory device allowing high-speed activation of in Semiconductor memory device allowing high-speed activation of in

1999-06-07

2000-02-29

Tran, Andrew Q.

Static information storage and retrieval

Powering

Conservation of power

365226, 365 63, 36523003, 36523006, 365233, G11C 514

Patent

active

060317817

ABSTRACT:
Row decoders RD are provided corresponding to memory blocks, respectively. Row decoders RD each operate receiving an operating power supply voltage from a hierarchical power supply system constituted of a main power supply line and a sub power supply line. With the use of a bank activation signal ACT, the main power supply line and the sub power supply line for all the hierarchical power supply system short circuit and a voltage of the sub power supply line is recovered. Thereafter, the main power supply line and the sub power supply line are cut off for a row decoder RD of a non-selected memory block based on a block selection signal BS supplied through a decoding operation.

REFERENCES:
patent: 5734604 (1998-03-01), Akamatsu et al.
patent: 5764566 (1998-06-01), Akamatsu et al.
patent: 5822265 (1998-10-01), Zdenek
"Subthreshold-Current Reduction Circuits for Multi-Gigabit DRAM's", by T. Sakata et al., IEEE Journal of Solid-State Circuits, vol. 29, No. 7, Jul. 1994, pp 761-769.

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