Semiconductor memory device allowing fast successive selection o

Details Semiconductor memory device allowing fast successive selection o Semiconductor memory device allowing fast successive selection o

1997-11-10

2000-10-31

Zarabian, A.

Static information storage and retrieval

Read/write circuit

Data refresh

365233, G11C 1300

Patent

active

061412783

ABSTRACT:
A disturb mode control circuit designates a disturb mode for activating an internal cycle setting circuit in response to a predetermined state of an address signal at a terminal when a disturb mode designating signal applied from a control circuit is active. The activated internal cycle setting circuit continuously issues a clock signal having a predetermined period to the control circuit. In accordance with the mode detection signal applied from the disturb mode control circuit and the clock signal applied from the internal cycle setting circuit, the control circuit successively generates an internal address signal in synchronization with the clock signal applied from an internal address generating circuit for selecting the word line in a memory cell array.

REFERENCES:
patent: 5347491 (1994-09-01), Kagami
patent: 5477491 (1995-12-01), Shirai
patent: 5495452 (1996-02-01), Cha
patent: 5544120 (1996-08-01), Kuwagata

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