Semiconductor memory device allowing easy characteristics...

Details Semiconductor memory device allowing easy characteristics... Semiconductor memory device allowing easy characteristics...

2001-11-13

2002-12-31

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S194000, C365S233100, C365S222000

Reexamination Certificate

active

06501693

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device characterized in that a part of basic timings of operations of an internal memory cell array is asynchronous with the outside.
2. Description of the Background Art
In recent years, a memory of a large capacity is in demand conspicuously as a portable electronic device such as a portable telephone has more and more functionality.
As a memory of such a device, generally, a static random access memory (SRAM) is mainly used. In the case of realizing a memory of a large capacity by this SRAM, the cost of the memory forms a large proportion of the whole system. In order to avoid an increase in price of the device, therefore, an idea of using a dynamic random access memory (DRAM) of a low cost per unit bit of the memory in place of an SRAM has been generated.
For manufacturers of portable electronic devices each using an SRAM as a main memory of a system, it is difficult to newly assemble a control circuit of a refreshing operation into the system. Consequently, manufacturers have been being developing a new memory using a memory cell that is used in a dynamic random access memory but capable of transmitting/receiving data to/from the outside by a control similar to that of an SRAM.
To be specific, the memory is characterized in that a dynamic memory cell as employed in a DRAM is used as an internal memory cell, an external interface substantially the same as that in an SRAM is used, refreshing operation is controlled internally by the chip itself, and refreshing control does not have to be particularly performed from the outside.
In the specification, in the connection with the function, such a memory will be called a DRAM with a complete hidden refresh function.
FIG. 8
is a block diagram showing the configuration of a conventional DRAM
501
with the complete hidden refresh function.
Referring to
FIG. 8
, DRAM
501
with the complete hidden refresh function includes: an input terminal group
2
for receiving controls signals /CE, /OE, /WE, /LB, and /UB; a terminal group
4
to/from which data signals DQ
0
to DQ
7
are input/output; a terminal group
6
to/from which data signals DQ
8
to DQ
15
are input/output; a terminal group
8
to which address signals A
0
to An are input; a power supply terminal
10
to which a source potential VCC is supplied; and a ground terminal
12
to which a ground voltage GND is applied.
Control signal /CE is a chip enable signal for selecting DRAM
501
when DRAM
501
is accessed from the outside. Control signal /OE is an output enable signal for setting DRAM
501
into a read mode and making an output buffer active. Control signal /WE is a write enable signal for setting DRAM
501
into a write mode. Control signal /LB is a signal for making selection of inputting/outputting data from/to data terminal group
4
on a lower-bit side. Control signal /UB is a signal for making selection of inputting/outputting data from/to data terminal group
6
on an upper-bit side.
DRAM
501
further includes: a mode control circuit
14
for receiving the signals from input terminal group
2
and address signals A
0
to An and detecting a refresh stop mode; a refresh trigger generating circuit
16
for generating a refresh trigger signal REFCYC in accordance with an output of mode control circuit
14
; and a control clock generating circuit
522
for outputting a control clock corresponding to a predetermined operation mode to each block in accordance with the signals supplied from input terminal group
2
and refresh trigger signal REFCYC.
DRAM
501
further includes: a column address buffer
24
for receiving address signals A
0
to Am (where m denotes a natural number smaller than n) and transmitting them to the inside in accordance with an output of control clock generating circuit
522
; and a row address buffer
25
for receiving address signals Am+1 to An and transmitting them to the inside in accordance with an output of control clock generating circuit
522
.
DRAM
501
further includes: a row decoder
26
for receiving internal address signals IAm+1 to IAn output from row address buffer
25
in accordance with an output of control clock generating circuit
522
and selecting a word line WL; a column decoder
28
for receiving internal address signals IA
0
to IAm output from column address buffer
24
in accordance with an output of control clock generating circuit
522
and selecting a bit line BL; a memory cell array
32
including memory cells MC arranged in a matrix; and a sense amplifier band
30
for amplifying and reading an output of memory cell array
32
. Sense amplifier band
30
includes, but not shown, a plurality of sense amplifiers and a plurality of input/output circuits.
In
FIG. 8
, one word line WL, one bit line BL, and one memory cell MC out of the plural memory cells MC included in memory cell array
32
are shown representatively.
DRAM
501
further includes: a lower-bit side input buffer IBL for receiving data signals DQ
0
to DQ
7
from terminal group
4
in accordance with a lower-bit control signal LC output from control clock generating circuit
522
and transmitting them to sense amplifier band
30
; a lower-bit side output buffer OBL for receiving a signal from sense amplifier band
30
in accordance with control signal LC and outputting a data signal to terminal group
4
; an upper-bit side input buffer IBU for receiving data signals DQ
8
to DQ
15
from terminal group
6
in accordance with an upper-bit control signal UC output from control clock generating circuit
522
and transmitting the received signals to sense amplifier band
30
; and an upper-bit side output buffer OBU for outputting data read from sense amplifier band
30
to terminal group
6
in accordance with control signal UC.
Generally, in a static random access memory (SRAM), signals supplied from the outside can be easily controlled. Higher packing density of memory cells MC can be achieved by using dynamic memory cells at lower cost as compared with static memory cells. However, since dynamic memory cells hold information by charges accumulated in memory cells, refreshing operation has to be performed every predetermined period, and the control is complicated.
In DRAM
501
shown in
FIG. 8
, signals supplied from the outside are address signals and control signals similar to those of an SRAM. Consequently, a semiconductor memory of a large capacity, which can be easily controlled is realized by using simple controls supplied from the outside like those in an SRAM and internally using memory cells similar to those in a DRAM.
When a memory cell in the DRAM is not accessed for a predetermined period, however, refreshing is necessary. In a period of time during which an access is not made, refresh trigger generating circuit
16
instructs control clock generating circuit
522
to perform refreshing operation by signal REFCYC.
FIG. 9
is a circuit diagram showing the configuration of sense amplifier band
30
and memory cell MC in FIG.
8
.
Referring to
FIG. 9
, sense amplifier band
30
includes an equalize circuit BEQ, a sense amplifier SAK, and a column selection gate CSG per bit lines BL and ZBL. A memory cell MC is disposed in an intersecting point between a word line WLn provided in corresponding with each memory cell row and bit line BL or ZBL.
FIG. 9
shows one memory cell representatively.
Memory cell MC includes an N-channel MOS transistor MT provided between bit line ZBL and a storage node SN and having a gate connected to word line WLn, and a capacitor MQ having one end connected to storage node SN and the other end coupled to a cell plate potential.
Between bit lines BL and ZBL equalize circuit BEQ for equalizing the potential of bit line BL and that of bit line ZBL in accordance with an equalize signal BLEQ is provided.
Equalize circuit BEQ includes three transistors; N-channel MOS transistor which is made conductive according to an equalize signal BLEQ to ther

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