Semiconductor memory device adapted to a high-speed operation, a

Details Semiconductor memory device adapted to a high-speed operation, a Semiconductor memory device adapted to a high-speed operation, a

1996-08-27

1997-08-12

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

365 51, 36518904, 36523004, G11C 1300

Patent

active

056572743

ABSTRACT:
In a NOR-type mask ROM, only one of opposite ends of each subsidiary digit line is connected to each block selection MOS transistor. The block selection MOS transistors are alternately connected to one end and the other end of adjacent subsidiary digit lines. Each of the block selection MOS transistors has a source and a drain connected to the primary and the subsidiary digit lines so that a current path at a channel portion has a direction perpendicular to the block selection lines. A gate of each block selection MOS transistor is located directly under the block selection line and has a gate width wider than the width of the subsidiary digit line.

REFERENCES:
patent: 5499216 (1996-03-01), Yamamoto

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